From patchwork Fri Oct 25 10:17:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 13850439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7426AD0C5FA for ; Fri, 25 Oct 2024 10:23:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4HSV-00042e-BN; Fri, 25 Oct 2024 06:22:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4HSR-00040w-Ne for qemu-devel@nongnu.org; Fri, 25 Oct 2024 06:22:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4HSP-0000U0-42 for qemu-devel@nongnu.org; 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Fri, 25 Oct 2024 10:21:02 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.194.5]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 74225196BB7D; Fri, 25 Oct 2024 10:20:57 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 07/21] arm/cpu: Store aa64drf0/1 into the idregs array Date: Fri, 25 Oct 2024 12:17:26 +0200 Message-ID: <20241025101959.601048-8-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.263, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.697, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.h | 2 -- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 15 +++++---------- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu64.c | 33 +++++++++++++++++---------------- 8 files changed, 39 insertions(+), 47 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 45f315df7b..9b0d5157bf 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -874,30 +874,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >= 4 && + FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) != 0xf; } static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >= 5 && + FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) != 0xf; } static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >= 6 && + FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) != 0xf; } static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, DEBUGVER) >= 8; } static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; + return FIELD_SEX64_IDREG(&id->idregs, ID_AA64DFR0, DOUBLELOCK) >= 0; } static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 419dfde638..6954952d5f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1088,8 +1088,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; IdRegMap idregs; diff --git a/target/arm/internals.h b/target/arm/internals.h index e1aa1a63b9..02c57f546b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,7 +1002,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) static inline int arm_num_brps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, BRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } @@ -1016,7 +1016,7 @@ static inline int arm_num_brps(ARMCPU *cpu) static inline int arm_num_wrps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, WRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } @@ -1030,7 +1030,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) static inline int arm_num_ctx_cmps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, CTX_CMPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cbfb6df435..42664dbfc1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2348,8 +2348,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu); #endif } else { - cpu->isar.id_aa64dfr0 = - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 = 0; cpu->pmceid1 = 0; @@ -2401,19 +2400,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * try to access the non-existent system registers for them. */ /* FEAT_SPE (Statistical Profiling Extension) */ - cpu->isar.id_aa64dfr0 = - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMSVER, 0); /* FEAT_TRBE (Trace Buffer Extension) */ - cpu->isar.id_aa64dfr0 = - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ - cpu->isar.id_aa64dfr0 = - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEFILT, 0); cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ - cpu->isar.id_aa64dfr0 = - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEVER, 0); cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 594778a031..85f581edb7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -630,7 +630,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_isar6 = 0; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 = 0x10305106; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr = 0x3516d000; @@ -689,7 +689,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_isar6 = 0; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 = 0x10305106; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr = 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index fa04383921..c15b24933d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8915,12 +8915,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = cpu->isar.id_aa64dfr0 }, + .resetvalue = GET_IDREG(idregs, ID_AA64DFR0) }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = cpu->isar.id_aa64dfr1 }, + .resetvalue = GET_IDREG(idregs, ID_AA64DFR1) }, { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index c9b99bf5ee..7377e4a133 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -328,10 +328,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR0_EL1); + err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR1_EL1); err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1); err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1); err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 64473fc3c7..56f086cb28 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -91,8 +91,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar5 = 0x00011121; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); SET_IDREG(idregs, ID_AA64PFR1, 0); - cpu->isar.id_aa64dfr0 = 0x10305106; - cpu->isar.id_aa64dfr1 = 0; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); + SET_IDREG(idregs, ID_AA64DFR1, 0); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64ISAR1, 0); SET_IDREG(idregs, ID_AA64MMFR0, 0x00101122); @@ -242,7 +242,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->clidr = 0x82000023; cpu->ctr = 0x84448004; /* L1Ip = VIPT */ cpu->dcz_blocksize = 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull); @@ -330,7 +330,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 = 0x00011142; cpu->isar.id_isar5 = 0x00011121; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 = 0x10305106; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr = 0x3516d000; @@ -369,7 +369,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr = 0x82000023; cpu->ctr = 0x8444C004; cpu->dcz_blocksize = 4; - cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408ull), SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull); @@ -440,8 +440,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr = 0x30000180; SET_IDREG(idregs, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000000); - cpu->isar.id_aa64dfr0 = 0x0000000010305408; - cpu->isar.id_aa64dfr1 = 0x0000000000000000; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408), + SET_IDREG(idregs, ID_AA64DFR1, 0x0000000000000000), cpu->id_aa64afr0 = 0x0000000000000000; cpu->id_aa64afr1 = 0x0000000000000000; SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000001122); @@ -611,7 +611,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->clidr = 0x82000023; cpu->ctr = 0x8444c004; cpu->dcz_blocksize = 4; - cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull); @@ -686,8 +686,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize = 4; cpu->id_aa64afr0 = 0x00000000; cpu->id_aa64afr1 = 0x00000000; - cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; - cpu->isar.id_aa64dfr1 = 0x00000000; + SET_IDREG(idregs, ID_AA64DFR0, 0x000001f210305519ull), + SET_IDREG(idregs, ID_AA64DFR1, 0x00000000), SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */ SET_IDREG(idregs, ID_AA64ISAR1, 0x0111000001211032ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull); @@ -930,8 +930,9 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 = 0x000011f010305619ull; - cpu->isar.id_aa64dfr1 = 0; + SET_IDREG(idregs, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(idregs, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(idregs, ID_AA64DFR1, 0); cpu->id_aa64afr0 = 0; cpu->id_aa64afr1 = 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ @@ -1029,8 +1030,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 = 0x000011f210305619ull; - cpu->isar.id_aa64dfr1 = 0; + SET_IDREG(idregs, ID_AA64DFR0, 0x000011f210305619ull); + SET_IDREG(idregs, ID_AA64DFR1, 0); cpu->id_aa64afr0 = 0; cpu->id_aa64afr1 = 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */ @@ -1257,11 +1258,11 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ SET_IDREG(idregs, ID_AA64ZFR0, t); - t = cpu->isar.id_aa64dfr0; + t = GET_IDREG(idregs, ID_AA64DFR0); t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_aa64dfr0 = t; + SET_IDREG(idregs, ID_AA64DFR0, t); t = cpu->isar.id_aa64smfr0; t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */