| Message ID | 20241104125536.1236118-2-zhenzhong.duan@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | intel_iommu: Add missed sanity check for invalidae descriptor | expand |
Hi, lgtm Thanks cmd On 04/11/2024 13:55, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > According to VTD spec, Figure 11-22, Invalidation Queue Tail Register, > "When Descriptor Width (DW) field in Invalidation Queue Address Register > (IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved > and a value of 1 in the bit will result in invalidation queue error." > > Current code missed to send IQE event to guest, fix it. > > Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support") > Suggested-by: Yi Liu <yi.l.liu@intel.com> > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > --- > hw/i386/intel_iommu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 8612d0917b..1ecfe47963 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -2847,6 +2847,7 @@ static void vtd_handle_iqt_write(IntelIOMMUState *s) > if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) { > error_report_once("%s: RSV bit is set: val=0x%"PRIx64, > __func__, val); > + vtd_handle_inv_queue_error(s); > return; > } > s->iq_tail = VTD_IQT_QT(s->iq_dw, val); > -- > 2.34.1 >
On 2024/11/4 20:55, Zhenzhong Duan wrote: > According to VTD spec, Figure 11-22, Invalidation Queue Tail Register, > "When Descriptor Width (DW) field in Invalidation Queue Address Register > (IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved > and a value of 1 in the bit will result in invalidation queue error." > > Current code missed to send IQE event to guest, fix it. a nit: mention the spec revision as well since the Figure number may be modified. Reviewed-by: Yi Liu <yi.l.liu@intel.com> > > Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support") > Suggested-by: Yi Liu <yi.l.liu@intel.com> > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > --- > hw/i386/intel_iommu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 8612d0917b..1ecfe47963 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -2847,6 +2847,7 @@ static void vtd_handle_iqt_write(IntelIOMMUState *s) > if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) { > error_report_once("%s: RSV bit is set: val=0x%"PRIx64, > __func__, val); > + vtd_handle_inv_queue_error(s); > return; > } > s->iq_tail = VTD_IQT_QT(s->iq_dw, val);
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8612d0917b..1ecfe47963 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2847,6 +2847,7 @@ static void vtd_handle_iqt_write(IntelIOMMUState *s) if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) { error_report_once("%s: RSV bit is set: val=0x%"PRIx64, __func__, val); + vtd_handle_inv_queue_error(s); return; } s->iq_tail = VTD_IQT_QT(s->iq_dw, val);
According to VTD spec, Figure 11-22, Invalidation Queue Tail Register, "When Descriptor Width (DW) field in Invalidation Queue Address Register (IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved and a value of 1 in the bit will result in invalidation queue error." Current code missed to send IQE event to guest, fix it. Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support") Suggested-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> --- hw/i386/intel_iommu.c | 1 + 1 file changed, 1 insertion(+)