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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.01.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:01:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 27/54] accel/tcg: Return CPUTLBEntryFull not pointer in probe_access_internal Date: Thu, 14 Nov 2024 08:01:03 -0800 Message-ID: <20241114160131.48616-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Return a copy of the structure, not a pointer. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 84e7e633e3..41b2f76cc9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1364,7 +1364,7 @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, static int probe_access_internal(CPUState *cpu, vaddr addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, - void **phost, CPUTLBEntryFull **pfull, + void **phost, CPUTLBEntryFull *pfull, uintptr_t retaddr, bool check_mem_cbs) { uintptr_t index = tlb_index(cpu, mmu_idx, addr); @@ -1379,7 +1379,7 @@ static int probe_access_internal(CPUState *cpu, vaddr addr, 0, fault_size, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost = NULL; - *pfull = NULL; + memset(pfull, 0, sizeof(*pfull)); return TLB_INVALID_MASK; } @@ -1398,8 +1398,9 @@ static int probe_access_internal(CPUState *cpu, vaddr addr, } flags &= tlb_addr; - *pfull = full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags |= full->slow_flags[access_type]; + *pfull = *full; /* * Fold all "mmio-like" bits, and required plugin callbacks, to TLB_MMIO. @@ -1423,19 +1424,17 @@ int probe_access_full(CPUArchState *env, vaddr addr, int size, bool nonfault, void **phost, CPUTLBEntryFull *pfull, uintptr_t retaddr) { - CPUTLBEntryFull *full; int flags = probe_access_internal(env_cpu(env), addr, size, access_type, - mmu_idx, nonfault, phost, &full, retaddr, + mmu_idx, nonfault, phost, pfull, retaddr, true); /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { int dirtysize = size == 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, full, retaddr); + notdirty_write(env_cpu(env), addr, dirtysize, pfull, retaddr); flags &= ~TLB_NOTDIRTY; } - *pfull = *full; return flags; } @@ -1444,25 +1443,22 @@ int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, void **phost, CPUTLBEntryFull *pfull) { void *discard_phost; - CPUTLBEntryFull *full; + CPUTLBEntryFull discard_full; /* privately handle users that don't need full results */ phost = phost ? phost : &discard_phost; + pfull = pfull ? pfull : &discard_full; int flags = probe_access_internal(env_cpu(env), addr, size, access_type, - mmu_idx, true, phost, &full, 0, false); + mmu_idx, true, phost, pfull, 0, false); /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { int dirtysize = size == 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, full, 0); + notdirty_write(env_cpu(env), addr, dirtysize, pfull, 0); flags &= ~TLB_NOTDIRTY; } - if (pfull) { - *pfull = *full; - } - return flags; } @@ -1470,7 +1466,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { - CPUTLBEntryFull *full; + CPUTLBEntryFull full; int flags; g_assert(-(addr | TARGET_PAGE_MASK) >= size); @@ -1482,7 +1478,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr, int size, /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { int dirtysize = size == 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, full, retaddr); + notdirty_write(env_cpu(env), addr, dirtysize, &full, retaddr); flags &= ~TLB_NOTDIRTY; } @@ -1492,7 +1488,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr, int size, void *probe_access(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUTLBEntryFull *full; + CPUTLBEntryFull full; void *host; int flags; @@ -1513,12 +1509,12 @@ void *probe_access(CPUArchState *env, vaddr addr, int size, int wp_access = (access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ); cpu_check_watchpoint(env_cpu(env), addr, size, - full->attrs, wp_access, retaddr); + full.attrs, wp_access, retaddr); } /* Handle clean RAM pages. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, full, retaddr); + notdirty_write(env_cpu(env), addr, size, &full, retaddr); } } @@ -1528,7 +1524,7 @@ void *probe_access(CPUArchState *env, vaddr addr, int size, void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_idx) { - CPUTLBEntryFull *full; + CPUTLBEntryFull full; void *host; int flags; @@ -1552,7 +1548,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, void **hostp) { - CPUTLBEntryFull *full; + CPUTLBEntryFull full; void *p; (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, @@ -1562,7 +1558,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, return -1; } - if (full->lg_page_size < TARGET_PAGE_BITS) { + if (full.lg_page_size < TARGET_PAGE_BITS) { return -1; }