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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.02.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:02:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 34/54] target/alpha: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:10 -0800 Message-ID: <20241114160131.48616-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/alpha/cpu.h | 6 +++--- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 23 +++++++++++++++++------ 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 3556d3227f..70331c0b83 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -449,9 +449,9 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, MMUAccessType access_type, uintptr_t retaddr); #else -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool alpha_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7..7bcc48420d 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -228,7 +228,7 @@ static const TCGCPUOps alpha_tcg_ops = { .record_sigsegv = alpha_cpu_record_sigsegv, .record_sigbus = alpha_cpu_record_sigbus, #else - .tlb_fill = alpha_cpu_tlb_fill, + .tlb_fill_align = alpha_cpu_tlb_fill_align, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .cpu_exec_halt = alpha_cpu_has_work, .do_interrupt = alpha_cpu_do_interrupt, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..26eadfe3ca 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -294,14 +294,21 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return (fail >= 0 ? -1 : phys); } -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool alpha_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra) { CPUAlphaState *env = cpu_env(cs); target_ulong phys; int prot, fail; + if (addr & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + alpha_cpu_do_unaligned_access(cs, addr, access_type, mmu_idx, ra); + } + fail = get_physical_address(env, addr, 1 << access_type, mmu_idx, &phys, &prot); if (unlikely(fail >= 0)) { @@ -314,11 +321,15 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull : access_type == MMU_DATA_STORE ? 1ull : /* access_type == MMU_INST_FETCH */ -1ull); - cpu_loop_exit_restore(cs, retaddr); + cpu_loop_exit_restore(cs, ra); } - tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr = phys; + out->prot = prot; + out->attrs = MEMTXATTRS_UNSPECIFIED; + out->lg_page_size = TARGET_PAGE_BITS; + return true; }