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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.02.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:02:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 38/54] target/m68k: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:14 -0800 Message-ID: <20241114160131.48616-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/m68k/cpu.h | 7 ++++--- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 22 +++++++++++++--------- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b5bbeedb7a..4401426a0b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -22,6 +22,7 @@ #define M68K_CPU_H #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "qemu/cpu-float.h" #include "cpu-qom.h" @@ -582,10 +583,10 @@ enum { #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); #ifndef CONFIG_USER_ONLY +bool m68k_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558a..5316cf8922 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -550,7 +550,7 @@ static const TCGCPUOps m68k_tcg_ops = { .restore_state_to_opc = m68k_restore_state_to_opc, #ifndef CONFIG_USER_ONLY - .tlb_fill = m68k_cpu_tlb_fill, + .tlb_fill_align = m68k_cpu_tlb_fill_align, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .cpu_exec_halt = m68k_cpu_has_work, .do_interrupt = m68k_cpu_do_interrupt, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c..1decb6f39c 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -950,9 +950,10 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) } } -bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType qemu_access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool m68k_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType qemu_access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUM68KState *env = cpu_env(cs); hwaddr physical; @@ -961,12 +962,14 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, int ret; target_ulong page_size; + memset(out, 0, sizeof(*out)); + out->attrs = MEMTXATTRS_UNSPECIFIED; + if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) { /* MMU disabled */ - tlb_set_page(cs, address & TARGET_PAGE_MASK, - address & TARGET_PAGE_MASK, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + out->phys_addr = address; + out->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + out->lg_page_size = TARGET_PAGE_BITS; return true; } @@ -985,8 +988,9 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, ret = get_physical_address(env, &physical, &prot, address, access_type, &page_size); if (likely(ret == 0)) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, mmu_idx, page_size); + out->phys_addr = physical; + out->prot = prot; + out->lg_page_size = ctz32(page_size); return true; }