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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9bab70sm1417926b3a.152.2024.11.14.08.05.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:05:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 46/54] target/s390x: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:22 -0800 Message-ID: <20241114160131.48616-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/s390x/s390x-internal.h | 7 ++++--- target/s390x/cpu.c | 4 ++-- target/s390x/tcg/excp_helper.c | 23 ++++++++++++++++++----- 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 825252d728..eb6fe24c9a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -278,9 +278,10 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, void s390_cpu_record_sigbus(CPUState *cs, vaddr address, MMUAccessType access_type, uintptr_t retaddr); #else -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool s390x_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr); G_NORETURN void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f301..4d0eb129e3 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -330,7 +330,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, * Instructions must be at even addresses. * This needs to be checked before address translation. */ - env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ + env->int_pgm_ilen = 2; /* see s390x_cpu_tlb_fill_align() */ tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } @@ -364,7 +364,7 @@ static const TCGCPUOps s390_tcg_ops = { .record_sigsegv = s390_cpu_record_sigsegv, .record_sigbus = s390_cpu_record_sigbus, #else - .tlb_fill = s390_cpu_tlb_fill, + .tlb_fill_align = s390x_cpu_tlb_fill_align, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .cpu_exec_halt = s390_cpu_has_work, .do_interrupt = s390_cpu_do_interrupt, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c0b692c9e..6d61032a4a 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -139,9 +139,10 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool s390x_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUS390XState *env = cpu_env(cs); target_ulong vaddr, raddr; @@ -151,6 +152,14 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + s390x_cpu_do_unaligned_access(cs, address, access_type, + mmu_idx, retaddr); + } + vaddr = address; if (mmu_idx < MMU_REAL_IDX) { @@ -177,8 +186,12 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); - tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); + + memset(out, 0, sizeof(*out)); + out->phys_addr = raddr; + out->prot = prot; + out->lg_page_size = TARGET_PAGE_BITS; + out->attrs = MEMTXATTRS_UNSPECIFIED; return true; } if (probe) {