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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72477120aa5sm2280879b3a.79.2024.11.15.21.39.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 21:39:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH RISU] risugen/aarch64: SMULH and UMULH require ra == 31 Date: Fri, 15 Nov 2024 21:39:18 -0800 Message-ID: <20241116053918.420404-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Do not generate ra other than 31, as it is UNPREDICTABLE whether the instruction will trap as invalid. Signed-off-by: Richard Henderson --- aarch64.risu | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/aarch64.risu b/aarch64.risu index 8f08cd0..87d9c72 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -1887,7 +1887,7 @@ SMSUBL A64 1 00 11011 001 rm:5 1 ra:5 rn:5 rd:5 \ SMNEGL A64 1 00 11011 001 rm:5 1 11111 rn:5 rd:5 -SMULH A64 1 00 11011 010 rm:5 0 ra:5 rn:5 rd:5 +SMULH A64 1 00 11011 010 rm:5 0 11111 rn:5 rd:5 UMADDL A64 1 00 11011 101 rm:5 0 ra:5 rn:5 rd:5 \ !constraints { $ra != 31; } @@ -1899,7 +1899,7 @@ UMSUBL A64 1 00 11011 101 rm:5 1 ra:5 rn:5 rd:5 \ UMNEGL A64 1 00 11011 101 rm:5 1 11111 rn:5 rd:5 -UMULH A64 1 00 11011 110 rm:5 0 ra:5 rn:5 rd:5 +UMULH A64 1 00 11011 110 rm:5 0 11111 rn:5 rd:5 # - Logical (shifted register) # 31|30 29| 28 27 26 25 24 |23 22| 21| 20 16 15 10 9 5 4 0