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[37.6.161.27]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa20df508f8sm337078666b.63.2024.11.16.10.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 10:15:51 -0800 (PST) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-rust@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Gustavo Romero , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Pierrick Bouvier , Richard Henderson Subject: [PATCH v1] rust/pl011: Fix DeviceID reads Date: Sat, 16 Nov 2024 20:15:47 +0200 Message-ID: <20241116181549.3430225-1-manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org DeviceId, which maps the peripheral and PCell registers of a PL011 device, was not treating each register value as a 32 bit value. Change DeviceId enum to return register values via constified getter functions instead of leveraging the std::ops::Index<_> trait. Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 79 +++++++++++++++++++++++++------- rust/hw/char/pl011/src/lib.rs | 22 ++++++++- 2 files changed, 83 insertions(+), 18 deletions(-) base-commit: 43f2def68476697deb0d119cbae51b20019c6c86 diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 2a85960b81..98dd97dbfd 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -5,7 +5,7 @@ use core::ptr::{addr_of, addr_of_mut, NonNull}; use std::{ ffi::CStr, - os::raw::{c_int, c_uchar, c_uint, c_void}, + os::raw::{c_int, c_uint, c_void}, }; use qemu_api::{ @@ -32,6 +32,7 @@ /// QEMU sourced constant. pub const PL011_FIFO_DEPTH: usize = 16_usize; +/// State enum that represents the values of the peripheral and PCell registers of a PL011 device. #[derive(Clone, Copy, Debug)] enum DeviceId { #[allow(dead_code)] @@ -39,20 +40,55 @@ enum DeviceId { Luminary, } -impl std::ops::Index for DeviceId { - type Output = c_uchar; - - fn index(&self, idx: hwaddr) -> &Self::Output { - match self { - Self::Arm => &Self::PL011_ID_ARM[idx as usize], - Self::Luminary => &Self::PL011_ID_LUMINARY[idx as usize], - } - } -} - impl DeviceId { - const PL011_ID_ARM: [c_uchar; 8] = [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1]; - const PL011_ID_LUMINARY: [c_uchar; 8] = [0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1]; + /// Value of `UARTPeriphID0` register, which contains the `PartNumber0` value. + const fn uart_periph_id0(self) -> u64 { + 0x11 + } + + /// Value of `UARTPeriphID1` register, which contains the `Designer0` and `PartNumber1` values. + const fn uart_periph_id1(self) -> u64 { + (match self { + Self::Arm => 0x10, + Self::Luminary => 0x00, + }) as u64 + } + + /// Value of `UARTPeriphID2` register, which contains the `Revision` and `Designer1` values. + const fn uart_periph_id2(self) -> u64 { + (match self { + Self::Arm => 0x14, + Self::Luminary => 0x18, + }) as u64 + } + + /// Value of `UARTPeriphID3` register, which contains the `Configuration` value. + const fn uart_periph_id3(self) -> u64 { + (match self { + Self::Arm => 0x0, + Self::Luminary => 0x1, + }) as u64 + } + + /// Value of `UARTPCellID0` register. + const fn uart_pcell_id0(self) -> u64 { + 0x0d + } + + /// Value of `UARTPCellID1` register. + const fn uart_pcell_id1(self) -> u64 { + 0xf0 + } + + /// Value of `UARTPCellID2` register. + const fn uart_pcell_id2(self) -> u64 { + 0x05 + } + + /// Value of `UARTPCellID3` register. + const fn uart_pcell_id3(self) -> u64 { + 0xb1 + } } #[repr(C)] @@ -182,9 +218,14 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow { - u64::from(self.device_id[(offset - 0xfe0) >> 2]) - } + Ok(PeriphID0) => self.device_id.uart_periph_id0(), + Ok(PeriphID1) => self.device_id.uart_periph_id1(), + Ok(PeriphID2) => self.device_id.uart_periph_id2(), + Ok(PeriphID3) => self.device_id.uart_periph_id3(), + Ok(PCellID0) => self.device_id.uart_pcell_id0(), + Ok(PCellID1) => self.device_id.uart_pcell_id1(), + Ok(PCellID2) => self.device_id.uart_pcell_id2(), + Ok(PCellID3) => self.device_id.uart_pcell_id3(), Err(_) => { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); 0 @@ -236,6 +277,10 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { use RegisterOffset::*; let value: u32 = value as u32; match RegisterOffset::try_from(offset) { + Ok(PeriphID0) | Ok(PeriphID1) | Ok(PeriphID2) | Ok(PeriphID3) | Ok(PCellID0) + | Ok(PCellID1) | Ok(PCellID2) | Ok(PCellID3) => { + // Ignore writes to read-only registers. + } Err(_bad_offset) => { eprintln!("write bad offset {offset} value {value}"); } diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index cd0a49acb9..1f305aa13f 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -111,6 +111,22 @@ pub enum RegisterOffset { /// DMA control Register #[doc(alias = "UARTDMACR")] DMACR = 0x048, + #[doc(alias = "UARTPeriphID0")] + PeriphID0 = 0xFE0, + #[doc(alias = "UARTPeriphID1")] + PeriphID1 = 0xFE4, + #[doc(alias = "UARTPeriphID2")] + PeriphID2 = 0xFE8, + #[doc(alias = "UARTPeriphID3")] + PeriphID3 = 0xFEC, + #[doc(alias = "UARTPCellID0")] + PCellID0 = 0xFF0, + #[doc(alias = "UARTPCellID1")] + PCellID1 = 0xFF4, + #[doc(alias = "UARTPCellID2")] + PCellID2 = 0xFF8, + #[doc(alias = "UARTPCellID3")] + PCellID3 = 0xFFC, ///// Reserved, offsets `0x04C` to `0x07C`. //Reserved = 0x04C, } @@ -137,7 +153,11 @@ const fn _assert_exhaustive(val: RegisterOffset) { } } } - case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, MIS, ICR, DMACR } + case! { + DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, MIS, ICR, DMACR, + PeriphID0, PeriphID1, PeriphID2, PeriphID3, + PCellID0, PCellID1, PCellID2, PCellID3, + } } }