From patchwork Sun Nov 17 14:39:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gao Shiyuan X-Patchwork-Id: 13877863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CC52D68BFA for ; Sun, 17 Nov 2024 14:41:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tCgSa-000788-7p; Sun, 17 Nov 2024 09:41:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tCgSW-00077m-8u for qemu-devel@nongnu.org; Sun, 17 Nov 2024 09:41:04 -0500 Received: from mx22.baidu.com ([220.181.50.185] helo=baidu.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tCgSS-0002o2-PX for qemu-devel@nongnu.org; Sun, 17 Nov 2024 09:41:03 -0500 To: , , , CC: , Subject: [PATCH 1/1] pcie-root-port: Fast PCIe root ports for new machine Date: Sun, 17 Nov 2024 22:39:17 +0800 Message-ID: <20241117143917.41403-1-gaoshiyuan@baidu.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-Originating-IP: [10.127.73.8] X-ClientProxiedBy: BC-MAIL-EX01.internal.baidu.com (172.31.51.41) To bjkjy-mail-ex26.internal.baidu.com (172.31.50.42) X-FEAS-Client-IP: 172.31.51.43 X-FE-Policy-ID: 52:10:53:SYSTEM Received-SPF: pass client-ip=220.181.50.185; envelope-from=gaoshiyuan@baidu.com; helo=baidu.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Gao Shiyuan X-Patchwork-Original-From: Gao Shiyuan via From: Gao Shiyuan Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some hardware devices now support PCIe 5.0, so change the default speed of the PCIe root port on new machine types. For passthrough Nvidia H20, this will be able to increase the h2d/d2h bandwidth ~17%. Origin: [CUDA Bandwidth Test] - Starting... Running on... Device 0: NVIDIA H20 Quick Mode Host to Device Bandwidth, 1 Device(s) PINNED Memory Transfers Transfer Size (Bytes) Bandwidth(MB/s) 33554432 45915.4 Device to Host Bandwidth, 1 Device(s) PINNED Memory Transfers Transfer Size (Bytes) Bandwidth(MB/s) 33554432 45980.3 Device to Device Bandwidth, 1 Device(s) PINNED Memory Transfers Transfer Size (Bytes) Bandwidth(MB/s) 33554432 1842886.8 Result = PASS With this patch: [CUDA Bandwidth Test] - Starting... Running on... Device 0: NVIDIA H20 Quick Mode Host to Device Bandwidth, 1 Device(s) PINNED Memory Transfers Transfer Size (Bytes) Bandwidth(MB/s) 33554432 53682.0 Device to Host Bandwidth, 1 Device(s) PINNED Memory Transfers Transfer Size (Bytes) Bandwidth(MB/s) 33554432 53766.0 Device to Device Bandwidth, 1 Device(s) PINNED Memory Transfers Transfer Size (Bytes) Bandwidth(MB/s) 33554432 1842555.1 Result = PASS Signed-off-by: Gao Shiyuan --- hw/core/machine.c | 1 + hw/pci-bridge/gen_pcie_root_port.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index a35c4a8fae..afef55626d 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -38,6 +38,7 @@ GlobalProperty hw_compat_9_1[] = { { TYPE_PCI_DEVICE, "x-pcie-ext-tag", "false" }, + { "pcie-root-port", "x-speed", "16" }, }; const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1); diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index 784507c826..c24ce1f2d1 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -142,7 +142,7 @@ static Property gen_rp_props[] = { DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, - speed, PCIE_LINK_SPEED_16), + speed, PCIE_LINK_SPEED_32), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), DEFINE_PROP_END_OF_LIST()