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Tue, 26 Nov 2024 06:01:39 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a3asm13310362f8f.66.2024.11.26.06.01.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:01:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH v3 14/16] target/mips: Convert microMIPS LI opcode to decodetree Date: Tue, 26 Nov 2024 15:00:00 +0100 Message-ID: <20241126140003.74871-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Once the xlat() and simm7() helpers are added, the decoding is trivial. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/micromips16.decode | 9 +++++++++ target/mips/tcg/micromips_translate.c | 19 +++++++++++++++++++ target/mips/tcg/micromips_translate.c.inc | 12 +----------- 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode index d341da16b04..fdc3b131c9c 100644 --- a/target/mips/tcg/micromips16.decode +++ b/target/mips/tcg/micromips16.decode @@ -9,3 +9,12 @@ # (Document Number: MD00582) # microMIPS64 Instruction Set # (Document Number: MD00594) + +&rd_imm rd imm + +%xlat_rd 7:3 !function=xlat +%simm7 0:7 !function=simm7 + +@rd_imm7 ...... ... ....... &rd_imm rd=%xlat_rd imm=%simm7 + +LI 111011 ... ....... @rd_imm7 # LI16 diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c index f0b5dbf655d..198eb466057 100644 --- a/target/mips/tcg/micromips_translate.c +++ b/target/mips/tcg/micromips_translate.c @@ -9,11 +9,23 @@ #include "qemu/osdep.h" #include "translate.h" +static int xlat(DisasContext *ctx, int x) +{ + static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + + return map[x]; +} + static inline int plus_1(DisasContext *ctx, int x) { return x + 1; } +static inline int simm7(DisasContext *ctx, int x) +{ + return x == 0x7f ? -1 : x; +} + /* Include the auto-generated decoders. */ #include "decode-micromips16.c.inc" #include "decode-micromips32.c.inc" @@ -22,3 +34,10 @@ static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } + +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a) +{ + gen_li(ctx, a->rd, a->imm); + + return true; +} diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 73394554509..cb98d6af7e4 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -113,7 +113,6 @@ enum { BLTZALC = 0x38, BLTUC = 0x38, SW16 = 0x3a, - LI16 = 0x3b, JALX32 = 0x3c, JAL32 = 0x3d, BLEZC = 0x3d, @@ -3004,7 +3003,7 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) case 2: /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */ case 3: - /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ + /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16 */ if (ctx->hflags & MIPS_HFLAG_BDS32) { gen_reserved_instruction(ctx); return 2; @@ -3214,15 +3213,6 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; - case LI16: - { - int reg = mmreg(uMIPS_RD(ctx->opcode)); - int imm = ZIMM(ctx->opcode, 0, 7); - - imm = (imm == 0x7f ? -1 : imm); - tcg_gen_movi_tl(cpu_gpr[reg], imm); - } - break; case RES_29: case RES_31: case RES_39: