[v3,16/16] target/mips: Convert nanoMIPS LI opcodes to decodetree

Commit Message

Philippe Mathieu-Daudé Nov. 26, 2024, 2 p.m. UTC

Signed-off-by: Philippe Mathieu-Daudé <[e-mail]>
---
 target/mips/tcg/nanomips16.decode        |  8 ++++++++
 target/mips/tcg/nanomips48.decode        |  8 ++++++++
 target/mips/tcg/nanomips_translate.c     | 21 +++++++++++++++++++++
 target/mips/tcg/nanomips_translate.c.inc | 17 -----------------
 4 files changed, 37 insertions(+), 17 deletions(-)

Patch

diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode
index 81fdc68e98b..12815161d9c 100644
--- a/target/mips/tcg/nanomips16.decode
+++ b/target/mips/tcg/nanomips16.decode
@@ -6,3 +6,11 @@ 
 #
 # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
 #            (Document Number: MD01247)
+
+&rd_imm             rd imm not_in_nms
+
+%s_eu               0:s7 !function=s_eu
+
+@rt3_s          ...... rd:3 .......         &rd_imm         imm=%s_eu
+
+LI              110100 ... .......          @rt3_s          not_in_nms=0        # LI[16]
diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode
index 696cc15607a..778bff4ec06 100644
--- a/target/mips/tcg/nanomips48.decode
+++ b/target/mips/tcg/nanomips48.decode
@@ -6,3 +6,11 @@ 
 #
 # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
 #            (Document Number: MD01247)
+
+&rd_imm     rd  imm not_in_nms                                       !extern
+
+%imm        16:16 0:s16
+
+@rd_imm     ...... rd:5  ..... ................ ................    &rd_imm imm=%imm
+
+LI          011000 ..... 00000 ................ ................    @rd_imm not_in_nms=1
diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c
index 3e77fcd23d3..aee0606e4d4 100644
--- a/target/mips/tcg/nanomips_translate.c
+++ b/target/mips/tcg/nanomips_translate.c
@@ -9,14 +9,35 @@ 
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static inline int s_eu(DisasContext *ctx, int x)
+{
+    return x == 0x7f ? -1 : x;
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-nanomips16.c.inc"
 #include "decode-nanomips32.c.inc"
 #include "decode-nanomips48.c.inc"
 
+static inline void check_nms(DisasContext *ctx, bool not_in_nms)
+{
+    if (not_in_nms && unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
+        gen_reserved_instruction(ctx);
+    }
+}
+
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
     gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 
     return true;
 }
+
+static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
+{
+    check_nms(ctx, a->not_in_nms);
+
+    gen_li(ctx, a->rd, a->imm);
+
+    return true;
+}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 0627f01c19e..e3d81d9e15b 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -57,7 +57,6 @@  enum {
 
     NM_POOL32S      = 0x30,
     NM_P_BRI        = 0x32,
-    NM_LI16         = 0x34,
     NM_SWGP16       = 0x35,
     NM_P16_BR       = 0x36,
 
@@ -86,7 +85,6 @@  enum {
 
 /* P48I instruction pool */
 enum {
-    NM_LI48        = 0x00,
     NM_ADDIU48     = 0x01,
     NM_ADDIUGP48   = 0x02,
     NM_ADDIUPC48   = 0x03,
@@ -3664,12 +3662,6 @@  static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
             target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
             switch (extract32(ctx->opcode, 16, 5)) {
-            case NM_LI48:
-                check_nms(ctx);
-                if (rt != 0) {
-                    tcg_gen_movi_tl(cpu_gpr[rt], addr_off);
-                }
-                break;
             case NM_ADDIU48:
                 check_nms(ctx);
                 if (rt != 0) {
@@ -4620,15 +4612,6 @@  static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
             break;
         }
         break;
-    case NM_LI16:
-        {
-            imm = extract32(ctx->opcode, 0, 7);
-            imm = (imm == 0x7f ? -1 : imm);
-            if (rt != 0) {
-                tcg_gen_movi_tl(cpu_gpr[rt], imm);
-            }
-        }
-        break;
     case NM_ANDI16:
         {
             uint32_t u = extract32(ctx->opcode, 0, 4);