| Message ID | 20241128104310.3452934-12-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | fpu: Make pickNaNMulAdd behaviour runtime selected | expand |
On 11/28/24 04:42, Peter Maydell wrote: > Set the FloatInfZeroNaNRule explicitly for the x86 target. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/i386/tcg/fpu_helper.c | 7 +++++++ > fpu/softfloat-specialize.c.inc | 2 +- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c > index 53b49bb2977..e9de084a96d 100644 > --- a/target/i386/tcg/fpu_helper.c > +++ b/target/i386/tcg/fpu_helper.c > @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) > */ > set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); > set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); > + /* > + * Only SSE has multiply-add instructions. > + * TODO: this might be wrong, as we never implemented any x86-specific > + * handling for the NaN case for multiply-add. This needs to be checked > + * against the manual. > + */ > + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); This is correct. Section 14.5.2 Fused-Multiply-ADD (FMA) Numeric Behavior has table 14-17 FMA Numeric Behavior. It boils down to selecting the first NaN from A * B + C. Row 3 specifically documents C as the result for A and B both in {0, Finite, Inf}, which includes the infzero case. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb2977..e9de084a96d 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. + * TODO: this might be wrong, as we never implemented any x86-specific + * handling for the NaN case for multiply-add. This needs to be checked + * against the manual. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19402d..ad4f7096d09 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c'
Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/i386/tcg/fpu_helper.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-)