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Fri, 29 Nov 2024 07:43:27 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d097e8dcefsm2003596a12.55.2024.11.29.07.43.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 3/3] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses Date: Fri, 29 Nov 2024 16:43:04 +0100 Message-ID: <20241129154304.34946-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Looking at htif_mm_ops[] read/write handlers, we notice they expect 32-bit values to accumulate into to the 'fromhost' and 'tohost' 64-bit variables. Explicit by setting the .impl min/max fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- Notes 1/ these variables belong to HTIFState but are declared statically! static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr; 2/ I believe a 64-bit implementation would simplify the logic. 3/ This is a non-QOM device model! Signed-off-by: Philippe Mathieu-Daudé --- hw/char/riscv_htif.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 3f84d8d6738..db69b5e3ca7 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -325,6 +325,10 @@ static const MemoryRegionOps htif_mm_ops = { .read = htif_mm_read, .write = htif_mm_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,