@@ -8077,38 +8077,21 @@ static bool trans_RMIF(DisasContext *s, arg_RMIF *a)
return true;
}
-/*
- * Evaluate into flags
- * 31 30 29 21 15 14 10 5 4 0
- * +--+--+--+-----------------+---------+----+---------+------+--+------+
- * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
- * +--+--+--+-----------------+---------+----+---------+------+--+------+
- */
-static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)
+static bool do_setf(DisasContext *s, int rn, int shift)
{
- int o3_mask = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int o2 = extract32(insn, 15, 6);
- int sz = extract32(insn, 14, 1);
- int sf_op_s = extract32(insn, 29, 3);
- TCGv_i32 tmp;
- int shift;
+ TCGv_i32 tmp = tcg_temp_new_i32();
- if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||
- !dc_isar_feature(aa64_condm_4, s)) {
- unallocated_encoding(s);
- return;
- }
- shift = sz ? 16 : 24; /* SETF16 or SETF8 */
-
- tmp = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn));
tcg_gen_shli_i32(cpu_NF, tmp, shift);
tcg_gen_shli_i32(cpu_VF, tmp, shift - 1);
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF);
+ return true;
}
+TRANS_FEAT(SETF8, aa64_condm_4, do_setf, a->rn, 24)
+TRANS_FEAT(SETF16, aa64_condm_4, do_setf, a->rn, 16)
+
/* Conditional compare (immediate / register)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
@@ -8277,30 +8260,12 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
{
int op1 = extract32(insn, 28, 1);
int op2 = extract32(insn, 21, 4);
- int op3 = extract32(insn, 10, 6);
if (!op1) {
goto do_unallocated;
}
switch (op2) {
- case 0x0:
- switch (op3) {
- case 0x02: /* Evaluate into flags */
- case 0x12:
- case 0x22:
- case 0x32:
- disas_evaluate_into_flags(s, insn);
- break;
-
- default:
- case 0x00: /* Add/subtract (with carry) */
- case 0x01: /* Rotate right into flags */
- case 0x21:
- goto do_unallocated;
- }
- break;
-
case 0x2: /* Conditional compare */
disas_cc(s, insn); /* both imm and reg forms */
break;
@@ -8311,6 +8276,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
default:
do_unallocated:
+ case 0x0:
case 0x6: /* Data-processing */
case 0x8 ... 0xf: /* (3 source) */
unallocated_encoding(s);
@@ -757,6 +757,10 @@ SBCS . 11 11010000 ..... 000000 ..... ..... @rrr_sf
RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4
# Evaluate into flags
+
+SETF8 0 01 11010000 00000 000010 rn:5 01101
+SETF16 0 01 11010000 00000 010010 rn:5 01101
+
# Conditional compare (regster)
# Conditional compare (immediate)
# Conditional select
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate-a64.c | 48 +++++----------------------------- target/arm/tcg/a64.decode | 4 +++ 2 files changed, 11 insertions(+), 41 deletions(-)