Message ID | 20241203034932.25185-2-fea.wang@sifive.com (mailing list archive) |
---|---|
State | New |
Headers | show
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Mon, 02 Dec 2024 19:38:07 -0800 (PST) Received: from hsinchu36-syssw02.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21566732e1fsm47111135ad.134.2024.12.02.19.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 19:38:07 -0800 (PST) From: "Fea.Wang" <fea.wang@sifive.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, "Fea.Wang" <fea.wang@sifive.com>, Frank Chang <frank.chang@sifive.com>, Jim Shu <jim.shu@sifive.com> Subject: [PATCH v5 1/6] target/riscv: Add svukte extension capability variable Date: Tue, 3 Dec 2024 11:49:27 +0800 Message-Id: <20241203034932.25185-2-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203034932.25185-1-fea.wang@sifive.com> References: <20241203034932.25185-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; 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Series |
Introduce svukte ISA extension
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expand
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diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..d8771ca641 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -84,6 +84,7 @@ struct RISCVCPUConfig { bool ext_svnapot; bool ext_svpbmt; bool ext_svvptc; + bool ext_svukte; bool ext_zdinx; bool ext_zaamo; bool ext_zacas;