[1/3] target/riscv: add a trap-misaligned-access property

Commit Message

Frederic Konrad Dec. 11, 2024, 9:19 p.m. UTC

On riscv target, misaligned accesses are either authorized and implemented in
hardware, or unimplemented and generate a trap to be implemented in software.

At the moment misaligned accesses for rvi just succeed, the intention of this
new property is to let the user choose to have a trap when a misaligned access
happens.

Signed-off-by: Frederic Konrad <[e-mail]>
---
 target/riscv/cpu.c     | 5 +++++
 target/riscv/cpu_cfg.h | 1 +
 2 files changed, 6 insertions(+)

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..1696d3db2a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2697,6 +2697,11 @@  static Property riscv_cpu_properties[] = {
      * it with -x and default to 'false'.
      */
     DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
+    /*
+     * when set, misaligned accesses will generate a trap.
+     */
+    DEFINE_PROP_BOOL("trap-misaligned-access", RISCVCPU,
+                     cfg.trap_misaligned_access, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..cc560371a1 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -173,6 +173,7 @@  struct RISCVCPUConfig {
     bool pmp;
     bool debug;
     bool misa_w;
+    bool trap_misaligned_access;
 
     bool short_isa_string;