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Wed, 11 Dec 2024 15:20:33 -0600 From: Frederic Konrad To: CC: , , , , , , , , , Frederic Konrad Subject: [PATCH 3/3] target/riscv: fix the trap generation for conditional store Date: Wed, 11 Dec 2024 22:19:33 +0100 Message-ID: <20241211211933.198792-4-fkonrad@amd.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241211211933.198792-1-fkonrad@amd.com> References: <20241211211933.198792-1-fkonrad@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: fkonrad@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06A:EE_|DM4PR12MB6614:EE_ X-MS-Office365-Filtering-Correlation-Id: bc21a525-fb35-48c4-6851-08dd1a29a88d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: JMLHe6A9iGBANo0UsVxynjXJYj7vYJegRw1zEb6NSMGdV9VwySxVpknUgZkJH9kaLbD4Y91iWvl8yb4afCQLj/lzQgi3RKjstCt9VLc6x72CayUsMj2+AKaU+yM4XEOTzbxK1KzdPCQNREvx9RY+45N3vJEFazR3JmTeLD1L3NF32EqFAuvUbS1X/VxA2KcVFn3+FQQorm5iOXurt6er3OCMNa5aT0rxWdm41iQiq8RzjU9Gld3TpG/OLR9GyJp6K5yYFLeXmW74dVK41shSLOLi3hSeb8/zBTn8t0Bo3KBEFxidkbxVbYVQqP8HR8ILZoQvmHdjdbXP8x1Ae7bg7w9ybQ8l9TdD80sZrDAdmryHbzv+ixzuQnR24hAKmomupiF7MQyhg0OvvaO9AsnHFiUdGDCTmoHd1q9mg0pyBYifp9S/aegYRbrOI1lwRun8bzCk5FI34qMc9so2zYbwOFITlV2rlnItHYbkPqszYC7xeST+BZgb7h99fQM5rPZkNFlN2lMBAI3Tp5UJpIFnAOI3U3MOR2xNqmxrd2lVSGZKsINyhBvA6yGEPoQ1BBKy92uBY36Ep2Fqhcleb133MrDyBukCwVZOIwcLY4AN5dCYYIyGpNd0eQNtXoNY/lk1/52JxvsU7yEhAIeHOiNVWGCHpWd6rc3QdZLbPNCT8FlIznIdJdkYeydrq/96vIURPU6XMbWRcREBAV1CTdWBndeyvk5HMaUEoSDMuItFmQAIXiZooatSasGvBwpxyGM4uVyMh5QjYs8AeewEKpiGs7SLwvLN6lZv7fZ6w+lIPteP4Wb+LwxVZQ6Ix1WuVGVIGZnHXvg0qqf0lAFIsbwcX9AI5Rb1PTnDxZiPMqjm2iLy8tDhHX/wMpFl+Ezt6LZhBaorAihwdZ0bv3R0LC+zw4wTjAUt/Okb/U2/lypL+Y7FvDYGqoriLoIaL1+SUrx12ZtF4Dol7M5Hy3lltwpYsDb93cDtm9ofTx1w/WyCLox5C/ZHRT2THvRq029dQbTAu8gOzCUOWqBd3iTz0pnvcbiUIwsjRKJ7Jcu3e8KoQB1lRzDSZDoqurjHCMvgPaFPb+mxes1zTz3Kkc9q/Ll9KWoKx13ygVn5m/5y57GX/NX5TIrRbVJ68V9S79/W7d5aygQIN3ULA8oE15Y88Z8BQ4OmYKYc2TovUCa2FVwTy/734nAWUJKUj4I1k18Ewb6Vu4S7VSaCjmgeZg9ihUNRrHDAor5jmno3YnrkiLIJh5CbCya6nwRVrA4TpEQ7I5bbtb48vGmBdKtTuh7ogDV4/oOkXZZNLylf4N2LlLdZNOkNBjGEp84bhH+IJy92vGYVQpaP4kWxL3SDPG2Nm0/kib7GtpotWmg6jMv1XYb7GA5f3MVsYtUwamjrnnEBK4CsgQmW+60bJNAL4hXSvUrszX9mbunuohvleibZhKF/fX9IxZ3rCZ3lvbUnSkcTvJph X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2024 21:20:37.9674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc21a525-fb35-48c4-6851-08dd1a29a88d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6614 Received-SPF: permerror client-ip=2a01:111:f403:2418::631; envelope-from=Frederic.Konrad@amd.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.472, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From Unpriviledged ISA manual: "For LR and SC, the Zalrsc extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated." Here nothing checks that the address is naturally aligned, so this fixes that wrong behavior by raising address-misaligned exception if the address in rs1 is not naturally aligned. Signed-off-by: Frederic Konrad --- target/riscv/insn_trans/trans_rva.c.inc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 9cf3ae8019..30a047164c 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -58,11 +58,30 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest, src1, src2; + TCGv tmp = tcg_temp_new(); + TCGLabel *l3 = gen_new_label(); TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); decode_save_opc(ctx, 0); src1 = get_address(ctx, a->rs1, 0); + /* + * A misaligned store trap should be triggered even if the store should + * fail due to the reservation. + */ + tcg_gen_andi_tl(tmp, src1, ~((uint64_t)0) << memop_alignment_bits(mop)); + tcg_gen_brcond_tl(TCG_COND_EQ, tmp, src1, l3); + + /* + * Store the faulty address, and the actual PC. Then generate the + * exception. + */ + tcg_gen_st_tl(src1, tcg_env, offsetof(CPURISCVState, badaddr)); + gen_pc_plus_diff(cpu_pc, ctx, 0); + gen_helper_raise_exception(tcg_env, + tcg_constant_i32(RISCV_EXCP_STORE_AMO_ADDR_MIS)); + + gen_set_label(l3); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); /*