[RFC,04/11] target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_tl()

Commit Message

Mark Cave-Ayland Dec. 12, 2024, 3:14 p.m. UTC

To ensure that all memory stores are performed by gen_st_tl(), convert all
remaining users of tcg_gen_qemu_st_tl() with gen_st_tl().

Signed-off-by: Mark Cave-Ayland <[e-mail]>
---
 target/ppc/translate.c                     | 10 +++++-----
 target/ppc/translate/fixedpoint-impl.c.inc |  2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

Comments

Richard Henderson Dec. 12, 2024, 3:27 p.m. UTC | #1

On 12/12/24 09:14, Mark Cave-Ayland wrote:
> To ensure that all memory stores are performed by gen_st_tl(), convert all
> remaining users of tcg_gen_qemu_st_tl() with gen_st_tl().
> 
> Signed-off-by: Mark Cave-Ayland <[e-mail]>
> ---
>   target/ppc/translate.c                     | 10 +++++-----
>   target/ppc/translate/fixedpoint-impl.c.inc |  2 +-
>   2 files changed, 6 insertions(+), 6 deletions(-)

I think you could squash patches 1+2 and 3+4.
Introduce the function and use it everywhere; the patches are not large.

Reviewed-by: Richard Henderson <[e-mail]>


r~

Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index bf94f3a5de..4c47f97607 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2724,7 +2724,7 @@  static void glue(gen_, name##epx)(DisasContext *ctx)                          \
     gen_set_access_type(ctx, ACCESS_INT);                                     \
     EA = tcg_temp_new();                                                      \
     gen_addr_reg_index(ctx, EA);                                              \
-    tcg_gen_qemu_st_tl(                                                       \
+    gen_st_tl(ctx,                                                            \
         cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop);              \
 }
 
@@ -2980,7 +2980,7 @@  static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
     /* E.g. for fetch and increment bounded... */
     /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
     tcg_gen_movcond_tl(cond, u, t, t2, u, t);
-    tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
+    gen_st_tl(ctx, u, EA, ctx->mem_idx, memop);
 
     /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
     tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t,
@@ -3045,7 +3045,7 @@  static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
             }
             tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
                                cpu_gpr[(rt + 2) & 31], t0);
-            tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
+            gen_st_tl(ctx, t1, EA, ctx->mem_idx, memop);
             tcg_gen_mov_tl(dst, t0);
         }
         break;
@@ -3149,8 +3149,8 @@  static void gen_st_atomic(DisasContext *ctx, MemOp memop)
             gen_ld_tl(ctx, t2, ea_plus_s, ctx->mem_idx, memop);
             tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
             tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
-            tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
-            tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
+            gen_st_tl(ctx, s, EA, ctx->mem_idx, memop);
+            gen_st_tl(ctx, s2, ea_plus_s, ctx->mem_idx, memop);
         }
         break;
     default:
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 717e3f122f..6b2265bd8f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -35,7 +35,7 @@  static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
     ea = do_ea_calc(ctx, ra, displ);
     mop ^= ctx->default_tcg_memop_mask;
     if (store) {
-        tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+        gen_st_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
     } else {
         gen_ld_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
     }