@@ -7,17 +7,13 @@
#include "qemu/osdep.h"
#include "qemu/bitops.h"
-#include "hw/sysbus.h"
-#include "hw/loongarch/virt.h"
-#include "hw/pci-host/ls7a.h"
#include "hw/irq.h"
#include "hw/intc/loongarch_pch_pic.h"
-#include "hw/qdev-properties.h"
-#include "migration/vmstate.h"
#include "trace.h"
#include "qapi/error.h"
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
+ int level)
{
uint64_t val;
int irq;
@@ -45,7 +41,7 @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
static void pch_pic_irq_handler(void *opaque, int irq, int level)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
uint64_t mask = 1ULL << irq;
assert(irq < s->irq_num);
@@ -78,7 +74,7 @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
unsigned size)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
uint64_t val = 0;
uint32_t offset = addr & 0xfff;
@@ -136,7 +132,7 @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
uint32_t offset, old_valid, data = (uint32_t)value;
uint64_t old, int_mask;
offset = addr & 0xfff;
@@ -208,7 +204,7 @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
unsigned size)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
uint64_t val = 0;
uint32_t offset = addr & 0xfff;
@@ -236,7 +232,7 @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
uint32_t offset, data = (uint32_t)value;
offset = addr & 0xfff;
@@ -263,7 +259,7 @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
unsigned size)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
uint64_t val = 0;
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
int64_t offset_tmp;
@@ -292,7 +288,7 @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
int32_t offset_tmp;
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
@@ -360,7 +356,7 @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
static void loongarch_pch_pic_reset(DeviceState *d)
{
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
int i;
s->int_mask = -1;
@@ -894,7 +894,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
/* Add Extend I/O Interrupt Controller node */
fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
- pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
+ pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
num = VIRT_PCH_PIC_IRQ_NUM;
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
d = SYS_BUS_DEVICE(pch_pic);
@@ -24,8 +24,4 @@ struct LoongarchPICClass {
DeviceRealize parent_realize;
};
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
-#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
-
#endif /* HW_LOONGARCH_PCH_PIC_H */