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Tue, 24 Dec 2024 09:24:09 -0500 (EST) From: Jiaxun Yang Date: Tue, 24 Dec 2024 14:24:02 +0000 Subject: [PATCH v3 3/3] hw/loongarch/boot: Support 32bit boot code MIME-Version: 1.0 Message-Id: <20241224-la-booting-v3-3-a15bee060a43@flygoat.com> References: <20241224-la-booting-v3-0-a15bee060a43@flygoat.com> In-Reply-To: <20241224-la-booting-v3-0-a15bee060a43@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Bibo Mao , Jiaxun Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2526; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=ggos8KxnCEkX4dJrh0H4vnXnArwrCkYHe5wYIMmNqeE=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhvSsI6yBoms+/vw3e4OyTM2ZsMiTzbU/s85FV1helsz7P U9s33u7jlIWBjEuBlkxRZYQAaW+DY0XF1x/kPUHZg4rE8gQBi5OAZjIp1iGv6LZjK0OZoUswnuc awVL2azP3XxnfLdzPuPsaROet53UPs/IcH/h1a2l03Le9rw/OTH9t2wdg2h+kuFbhu7sz7nMs3f JswIA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass client-ip=202.12.124.155; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR instructions to prevent illegal instructions. Signed-off-by: Jiaxun Yang --- hw/loongarch/boot.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c index 9cb13c1f154cb15373d6fdcbcbac883e05472e62..0046ad3e424bdcc488db709945d7059749e0cdc3 100644 --- a/hw/loongarch/boot.c +++ b/hw/loongarch/boot.c @@ -22,7 +22,7 @@ unsigned memmap_entries; ram_addr_t initrd_offset; uint64_t initrd_size; -static void generate_secondary_boot_code(void *boot_code) +static void generate_secondary_boot_code(void *boot_code, bool is_64bit) { uint32_t *p = boot_code; @@ -36,7 +36,11 @@ static void generate_secondary_boot_code(void *boot_code) /* Clear mailbox. */ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */ - stl_p(p++, 0x06481da0); /* iocsrwr.d $zero, $t1 */ + if (is_64bit) { + stl_p(p++, 0x06481da0); /* iocsrwr.d $zero, $t1 */ + } else { + stl_p(p++, 0x064819a0); /* iocsrwr.w $zero, $t1 */ + } /* Enable IPI interrupt. */ stl_p(p++, 0x1400002c); /* lu12i.w $t0, 1(0x1) */ @@ -68,7 +72,11 @@ static void generate_secondary_boot_code(void *boot_code) /* Read mail buf and jump to specified entry. */ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */ - stl_p(p++, 0x06480dac); /* iocsrrd.d $t0, $t1 */ + if (is_64bit) { + stl_p(p++, 0x06480dac); /* iocsrrd.d $t0, $t1 */ + } else { + stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */ + } stl_p(p++, 0x00150181); /* move $ra, $t0 */ stl_p(p++, 0x4c000020); /* jirl $zero, $ra, 0 */ } @@ -383,7 +391,7 @@ static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info) /* Load slave boot code at pflash0 . */ void *boot_code = g_malloc0(VIRT_FLASH0_SIZE); - generate_secondary_boot_code(boot_code); + generate_secondary_boot_code(boot_code, is_la64(&lacpu->env)); rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE, VIRT_FLASH0_BASE); CPU_FOREACH(cs) {