diff mbox series

[v2,07/23] target/loongarch: Cast address to 64bit before DMW_64_VSEG shift

Message ID 20241226-la32-fixes1-v2-7-0414594f8cb5@flygoat.com (mailing list archive)
State New
Headers show
Series target/loongarch: LoongArch32 fixes 1 | expand

Commit Message

Jiaxun Yang Dec. 26, 2024, 9:19 p.m. UTC 
Avoid compiler warning on 32bit. This code path won't be taken anyway.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Richard Henderson Dec. 26, 2024, 9:28 p.m. UTC | #1 
On 12/26/24 13:19, Jiaxun Yang wrote:
> Avoid compiler warning on 32bit. This code path won't be taken anyway.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/cpu_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
> index 580362ac3e9ffbe6c8523cf57902dcda018ceed5..b8da136eb0554ba661a15e3069ee0d6bae61af86 100644
> --- a/target/loongarch/cpu_helper.c
> +++ b/target/loongarch/cpu_helper.c
> @@ -196,7 +196,7 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
>   
>       plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
>       if (is_la64(env)) {
> -        base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
> +        base_v = (uint64_t)address >> R_CSR_DMW_64_VSEG_SHIFT;
>       } else {
>           base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
>       }
> 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 580362ac3e9ffbe6c8523cf57902dcda018ceed5..b8da136eb0554ba661a15e3069ee0d6bae61af86 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -196,7 +196,7 @@  int get_physical_address(CPULoongArchState *env, hwaddr *physical,
 
     plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
     if (is_la64(env)) {
-        base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
+        base_v = (uint64_t)address >> R_CSR_DMW_64_VSEG_SHIFT;
     } else {
         base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
     }