| Message ID | 20250106054336.1878291-6-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Smrnmi support | expand |
On Mon, Jan 6, 2025 at 3:46 PM <frank.chang@sifive.com> wrote: > > From: Tommy Wu <tommy.wu@sifive.com> > > This adds the properties for ISA extension Smrnmi. > > Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set > mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all > interrupts will be disabled. Since our current OpenSBI does not > support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for > now. We can re-enable it once OpenSBI includes proper support for it. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Signed-off-by: Tommy Wu <tommy.wu@sifive.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/tcg/tcg-cpu.c | 9 +++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 29d530ad85..d9bc0d124e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > @@ -1621,6 +1622,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), > MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), > MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), > MULTI_EXT_CFG_BOOL("svade", ext_svade, false), > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index e03b409248..9cfdd68fdc 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1431,6 +1431,15 @@ static void riscv_init_max_cpu_extensions(Object *obj) > if (env->misa_mxl != MXL_RV32) { > isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); > } > + > + /* > + * ext_smrnmi requires OpenSBI changes that our current > + * image does not have. Disable it for now. > + */ > + if (cpu->cfg.ext_smrnmi) { > + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); > + qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); > + } > } > > static bool riscv_cpu_has_max_extensions(Object *cpu_obj) > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 29d530ad85..d9bc0d124e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), @@ -1621,6 +1622,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e03b409248..9cfdd68fdc 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1431,6 +1431,15 @@ static void riscv_init_max_cpu_extensions(Object *obj) if (env->misa_mxl != MXL_RV32) { isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } + + /* + * ext_smrnmi requires OpenSBI changes that our current + * image does not have. Disable it for now. + */ + if (cpu->cfg.ext_smrnmi) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); + qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); + } } static bool riscv_cpu_has_max_extensions(Object *cpu_obj)