[v2,47/81] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}

Message ID	20250107080112.1175095-48-richard.henderson@linaro.org (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 47/81] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} Date: Tue, 7 Jan 2025 00:00:38 -0800 Message-ID: <20250107080112.1175095-48-richard.henderson@linaro.org> In-Reply-To: <20250107080112.1175095-1-richard.henderson@linaro.org> References: <20250107080112.1175095-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	tcg: Merge _i32 and _i64 opcodes \| expand [RFC,v2,00/81] tcg: Merge _i32 and _i64 opcodes [v2,01/81] tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc [v2,02/81] tcg: Replace TCGOP_VECL with TCGOP_TYPE [v2,03/81] tcg: Move tcg_op_insert_{after, before} decls to tcg-internal.h [v2,04/81] tcg: Copy TCGOP_TYPE in tcg_op_insert_{after, before} [v2,05/81] tcg: Add TCGOP_FLAGS [v2,06/81] tcg: Add type and flags arguments to tcg_op_supported [v2,07/81] target/arm: Do not test TCG_TARGET_HAS_bitsel_vec [v2,08/81] target/arm: Use tcg_op_supported [v2,09/81] target/tricore: Use tcg_op_supported [v2,10/81] tcg: Add tcg_op_deposit_valid [v2,11/81] target/i386: Remove TCG_TARGET_extract_tl_valid [v2,12/81] target/i386: Use tcg_op_deposit_valid [v2,13/81] target/i386: Use tcg_op_supported [v2,14/81] tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS [v2,15/81] tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc [v2,16/81] tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc [v2,17/81] tcg: Move fallback tcg_can_emit_vec_op out of line [v2,18/81] tcg: Split out tcg-target-has.h and tcg-has.h [v2,19/81] tcg: Split out tcg-target-mo.h [v2,20/81] tcg: Use C_NotImplemented in tcg_target_op_def [v2,21/81] tcg: Change have_vec to has_type in tcg_op_supported [v2,22/81] tcg: Reorg process_op_defs [v2,23/81] tcg: Remove args_ct from TCGOpDef [v2,24/81] tcg: Constify tcg_op_defs [v2,25/81] tcg: Validate op supported in opcode_args_ct [v2,26/81] tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputs [v2,27/81] tcg: Pass type and flags to tcg_target_op_def [v2,28/81] tcg: Add TCGType argument to tcg_out_op [v2,29/81] tcg: Remove TCG_OPF_64BIT [v2,30/81] tcg: Drop implementation checks from tcg-opc.h [v2,31/81] tcg: Replace IMPLVEC with TCG_OPF_VECTOR [v2,32/81] tcg/mips: Expand bswap unconditionally [v2,33/81] tcg/i386: Handle all 8-bit extensions for i686 [v2,34/81] tcg/i386: Fold the ext{8, 16, 32}[us] cases into {s}extract [v2,35/81] tcg/aarch64: Provide TCG_TARGET_{s}extract_valid [v2,36/81] tcg/aarch64: Expand extract with offset 0 with andi [v2,37/81] tcg/arm: Add full [US]XT[BH] into {s}extract [v2,38/81] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract [v2,39/81] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract [v2,40/81] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract [v2,41/81] tcg/riscv64: Fold the ext{8, 16, 32}[us] cases into {s}extract [v2,42/81] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 [v2,43/81] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract [v2,44/81] tcg/sparc64: Use SRA, SRL for {s}extract_i64 [v2,45/81] tcg/tci: Provide TCG_TARGET_{s}extract_valid [v2,46/81] tcg/tci: Remove assertions for deposit and extract [v2,47/81] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} [v2,48/81] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} [v2,49/81] tcg: Remove INDEX_op_ext{8,16,32}* [v2,50/81] tcg: Add all_outop[] [v2,51/81] tcg: Merge INDEX_op_mov_{i32,i64} [v2,52/81] tcg: Convert add to TCGOutOpBinary [v2,53/81] tcg: Merge INDEX_op_add_{i32,i64} [v2,54/81] tcg: Convert and to TCGOutOpBinary [v2,55/81] tcg: Merge INDEX_op_and_{i32,i64} [v2,56/81] tcg/optimize: Fold andc with immediate to and [v2,57/81] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 [v2,58/81] tcg: Convert andc to TCGOutOpBinary [v2,59/81] tcg: Merge INDEX_op_andc_{i32,i64} [v2,60/81] tcg: Convert or to TCGOutOpBinary [v2,61/81] tcg: Merge INDEX_op_or_{i32,i64} [v2,62/81] tcg/optimize: Fold orc with immediate to or [v2,63/81] tcg: Convert orc to TCGOutOpBinary [v2,64/81] tcg: Merge INDEX_op_orc_{i32,i64} [v2,65/81] tcg: Convert xor to TCGOutOpBinary [v2,66/81] tcg: Merge INDEX_op_xor_{i32,i64} [v2,67/81] tcg/optimize: Fold eqv with immediate to xor [v2,68/81] tcg: Convert eqv to TCGOutOpBinary [v2,69/81] tcg: Merge INDEX_op_eqv_{i32,i64} [v2,70/81] tcg: Convert nand to TCGOutOpBinary [v2,71/81] tcg: Merge INDEX_op_nand_{i32,i64} [v2,72/81] tcg/loongarch64: Do not accept constant argument to nor [v2,73/81] tcg: Convert nor to TCGOutOpBinary [v2,74/81] tcg: Merge INDEX_op_nor_{i32,i64} [v2,75/81] tcg/arm: Fix constraints for sub [v2,76/81] tcg: Convert sub to TCGOutOpSubtract [v2,77/81] tcg: Merge INDEX_op_sub_{i32,i64} [v2,78/81] tcg: Convert neg to TCGOutOpUnary [v2,79/81] tcg: Merge INDEX_op_neg_{i32,i64} [v2,80/81] tcg: Convert not to TCGOutOpUnary [v2,81/81] tcg: Merge INDEX_op_not_{i32,i64}

diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 26ce65b6a5..43eaa2287c 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -32,8 +32,6 @@ #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 @@ -67,8 +65,6 @@ #define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h index d6ca35ed1a..7152dd6f5e 100644 --- a/tcg/arm/tcg-target-has.h +++ b/tcg/arm/tcg-target-has.h @@ -41,8 +41,6 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions -#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions -#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h index ad69f957a7..833ccc411a 100644 --- a/tcg/i386/tcg-target-has.h +++ b/tcg/i386/tcg-target-has.h @@ -44,8 +44,6 @@ #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 have_popcnt #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 @@ -79,8 +77,6 @@ #define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctpop_i64 have_popcnt #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h index ac7d2fcdf9..a15ab9cc28 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -16,8 +16,6 @@ #define TCG_TARGET_HAS_div2_i32 0 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 @@ -51,8 +49,6 @@ #define TCG_TARGET_HAS_div2_i64 0 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index e7914cc970..1bc14f65dd 100644 --- a/tcg/mips/tcg-target-has.h +++ b/tcg/mips/tcg-target-has.h @@ -80,8 +80,6 @@ extern bool use_mips32r2_instructions; /* optional instructions detected at runtime */ #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions @@ -96,8 +94,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h index d087189a77..fa9275264c 100644 --- a/tcg/ppc/tcg-target-has.h +++ b/tcg/ppc/tcg-target-has.h @@ -38,8 +38,6 @@ #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 @@ -74,8 +72,6 @@ #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index e890546c3a..5a39720ea9 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -16,8 +16,6 @@ #define TCG_TARGET_HAS_div2_i32 0 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i32 0 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -50,8 +48,6 @@ #define TCG_TARGET_HAS_div2_i64 0 #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 72b57407d4..f3965c7df5 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -47,8 +47,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 @@ -81,8 +79,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h index 2db461efed..4a621313b7 100644 --- a/tcg/sparc64/tcg-target-has.h +++ b/tcg/sparc64/tcg-target-has.h @@ -33,8 +33,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_deposit_i32 0 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 @@ -68,8 +66,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h index 8ed35be8c3..c93a98fb86 100644 --- a/tcg/tcg-has.h +++ b/tcg/tcg-has.h @@ -35,8 +35,6 @@ #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_add2_i64 0 @@ -56,16 +54,6 @@ #ifndef TCG_TARGET_deposit_i64_valid #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 #endif -#ifndef TCG_TARGET_extract_valid -#define TCG_TARGET_extract_valid(type, ofs, len) \ - ((type) == TCG_TYPE_I32 ? TCG_TARGET_HAS_extract_i32 \ - : TCG_TARGET_HAS_extract_i64) -#endif -#ifndef TCG_TARGET_sextract_valid -#define TCG_TARGET_sextract_valid(type, ofs, len) \ - ((type) == TCG_TYPE_I32 ? TCG_TARGET_HAS_sextract_i32 \ - : TCG_TARGET_HAS_sextract_i64) -#endif /* Only one of DIV or DIV2 should be defined. */ #if defined(TCG_TARGET_HAS_div_i32) diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index 2f45ad614f..7a176b1fe5 100644 --- a/tcg/tci/tcg-target-has.h +++ b/tcg/tci/tcg-target-has.h @@ -17,8 +17,6 @@ #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 1 -#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 @@ -41,8 +39,6 @@ #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 1 -#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/optimize.c b/tcg/optimize.c index cd8ad712c4..8c6303e3af 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2363,10 +2363,10 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) shr_opc = INDEX_op_shr_i32; neg_opc = INDEX_op_neg_i32; if (TCG_TARGET_extract_valid(TCG_TYPE_I32, sh, 1)) { - uext_opc = TCG_TARGET_HAS_extract_i32 ? INDEX_op_extract_i32 : 0; + uext_opc = INDEX_op_extract_i32; } if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, sh, 1)) { - sext_opc = TCG_TARGET_HAS_sextract_i32 ? INDEX_op_sextract_i32 : 0; + sext_opc = INDEX_op_sextract_i32; } break; case TCG_TYPE_I64: @@ -2376,10 +2376,10 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) shr_opc = INDEX_op_shr_i64; neg_opc = INDEX_op_neg_i64; if (TCG_TARGET_extract_valid(TCG_TYPE_I64, sh, 1)) { - uext_opc = TCG_TARGET_HAS_extract_i64 ? INDEX_op_extract_i64 : 0; + uext_opc = INDEX_op_extract_i64; } if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, sh, 1)) { - sext_opc = TCG_TARGET_HAS_sextract_i64 ? INDEX_op_sextract_i64 : 0; + sext_opc = INDEX_op_sextract_i64; } break; default: diff --git a/tcg/tcg.c b/tcg/tcg.c index 350ab5948e..76aefda514 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2195,6 +2195,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: + case INDEX_op_extract_i32: + case INDEX_op_sextract_i32: return true; case INDEX_op_negsetcond_i32: @@ -2213,10 +2215,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) return TCG_TARGET_HAS_rot_i32; case INDEX_op_deposit_i32: return TCG_TARGET_HAS_deposit_i32; - case INDEX_op_extract_i32: - return TCG_TARGET_HAS_extract_i32; - case INDEX_op_sextract_i32: - return TCG_TARGET_HAS_sextract_i32; case INDEX_op_extract2_i32: return TCG_TARGET_HAS_extract2_i32; case INDEX_op_add2_i32: @@ -2293,6 +2291,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_sar_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i64: return TCG_TARGET_REG_BITS == 64; case INDEX_op_negsetcond_i64: @@ -2311,10 +2311,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) return TCG_TARGET_HAS_rot_i64; case INDEX_op_deposit_i64: return TCG_TARGET_HAS_deposit_i64; - case INDEX_op_extract_i64: - return TCG_TARGET_HAS_extract_i64; - case INDEX_op_sextract_i64: - return TCG_TARGET_HAS_sextract_i64; case INDEX_op_extract2_i64: return TCG_TARGET_HAS_extract2_i64; case INDEX_op_extrl_i64_i32: diff --git a/tcg/tci.c b/tcg/tci.c index 39a68db287..30d912d75d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -657,18 +657,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; #endif -#if TCG_TARGET_HAS_extract_i32 case INDEX_op_extract_i32: tci_args_rrbb(insn, &r0, &r1, &pos, &len); regs[r0] = extract32(regs[r1], pos, len); break; -#endif -#if TCG_TARGET_HAS_sextract_i32 case INDEX_op_sextract_i32: tci_args_rrbb(insn, &r0, &r1, &pos, &len); regs[r0] = sextract32(regs[r1], pos, len); break; -#endif case INDEX_op_brcond_i32: tci_args_rl(insn, tb_ptr, &r0, &ptr); if ((uint32_t)regs[r0]) { @@ -868,18 +864,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; #endif -#if TCG_TARGET_HAS_extract_i64 case INDEX_op_extract_i64: tci_args_rrbb(insn, &r0, &r1, &pos, &len); regs[r0] = extract64(regs[r1], pos, len); break; -#endif -#if TCG_TARGET_HAS_sextract_i64 case INDEX_op_sextract_i64: tci_args_rrbb(insn, &r0, &r1, &pos, &len); regs[r0] = sextract64(regs[r1], pos, len); break; -#endif case INDEX_op_brcond_i64: tci_args_rl(insn, tb_ptr, &r0, &ptr); if (regs[r0]) {

[v2,47/81] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}

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