From patchwork Fri Jan 10 12:54:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13934528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF608E7719C for ; Fri, 10 Jan 2025 12:56:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWEYF-00050n-CS; Fri, 10 Jan 2025 07:55:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWEXZ-0004G1-No for qemu-devel@nongnu.org; Fri, 10 Jan 2025 07:55:07 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWEXV-0000zC-Cr for qemu-devel@nongnu.org; Fri, 10 Jan 2025 07:55:04 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso15486485e9.0 for ; Fri, 10 Jan 2025 04:54:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1736513696; x=1737118496; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8PN/V0WbuFw6HaJW1Nzyst7CrJezrXLSp+E+Q++VNOs=; b=DmlOqZojZ95ZAWmTy0V2afAA8BDDuvMTM25WhHPE2i6q7xOPMMUcUZ/7lI3QrjmHzp cCcwT9Pj/x4sizt+n67WeMUXeLIVm0pT5zYVw0VGDFSUO2svan+ntD7jU4UH4q/bTdl3 1087/9+qFC842My1wMOaocu9Wkbikw5yqyol9VPDEdaNgp9/oMyqnpIDofVMUzOWeCHF EAY+VHxv8+Cv2EhrysFQxtXxOVbz6vpcBmd7dKoTRvjfdHnxjIDCJJo01Uw2CMhzbfRi rA3vq98rkvK7GbUIX4y8vjcy10hMwLymlnETZiWntWoC9Xr2zS/36KvQF77bt7m6gfm3 X4sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736513696; x=1737118496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8PN/V0WbuFw6HaJW1Nzyst7CrJezrXLSp+E+Q++VNOs=; b=D02tAsx6iT0shjp070hXzjHW32Wurx1rWEB3SPEZesPgDl4O0nXRWbhMdk1eV8xDHb NQbw6YDANFmS9ky9jbom2mu55iT0t6DzTULLTFQ8SLsILG2nvTeJN9Z7ZnVX1zcvZRBM TZGto5ek2peRvKRY2Dta4wJJUEyOVNMdWPLZw+A0O6xBt8OIBLz5bWjoLp/YMBdA+5s7 CIs4alQ+XCWF94SPZkt0fHAoCWXk1vV48b/IydCjSJ5m4RqGvEcS64rWJzgNJQh4TZGt XEHKs90WPZmQWbmDiBfV+tBeoRISVPcs3lMS1X4yUev62dn/p49oZJOSJ5UQsc2632Ja ssxw== X-Forwarded-Encrypted: i=1; AJvYcCUQDdC28SdWc8I0hm8KiYP9nHeWMEEEpBLGVJoBOPPm6Am3QHFq9JUh/2JFtVzbLuKNg1BkotlyFw3S@nongnu.org X-Gm-Message-State: AOJu0YxZHouXwhWMOzygEeCESJ7gMvY5/y5Nm6/2K3NQgBXYZQWcX93K qNVCjWOUQDUP91pK3LSfQ/HUgZxEOXqLDHWhVYT47R0kCzpPbi/iaaWsJ48ERwE= X-Gm-Gg: ASbGncuutsxHZqrqHaWuvXNY3AoXe474Y7B7t+U39PRUMJiyT4I9JWMayBP3h/G8rIN TQNG4A8kNPxtB8b97ri+HN611GUUd//DAAZqTISbbvR7r5GllHJ/KgI4d8iS+HgxS13H4B9YN2i qfPZR/kPOU0WnDwDtkG6Idl/aiyHTJiW3RXdq+9NslpWQyDXAYuXO3MOPJcPHT7R6khfdGW1Bky 5e8+k7mJYMoF3v0RVReHC2vYSf0rL9NuxAPbbtH4DzGQid4+ZDcKohDpA== X-Google-Smtp-Source: AGHT+IEfvq9dZz2EoQ/kHnt5RxTA1kHEy8ZtCpCqpj+7g+pc91718HlrIqWkt4MITuzmsIwcoBtM3g== X-Received: by 2002:a05:600c:3143:b0:434:fbda:1f44 with SMTP id 5b1f17b1804b1-436e26a8c09mr92749015e9.19.1736513696304; Fri, 10 Jan 2025 04:54:56 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4c1c01sm4548921f8f.97.2025.01.10.04.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2025 04:54:55 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org, Frank Chang Subject: [PATCH v8 4/9] target/riscv: Implement Ssdbltrp exception handling Date: Fri, 10 Jan 2025 13:54:35 +0100 Message-ID: <20250110125441.3208676-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110125441.3208676-1-cleger@rivosinc.com> References: <20250110125441.3208676-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe470f646d..5540eb7f63 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -303,7 +303,7 @@ static const char * const riscv_excp_names[] = { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0a56163d73..a3acda4bc8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -701,6 +701,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP = 0x10, RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1eac0a0062..539ba327e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1951,6 +1951,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool virt = env->virt_enabled; bool write_gva = false; bool always_storeamo = (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); + bool vsmode_exc; uint64_t s; int mode; @@ -1965,6 +1966,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1ULL << cause)); bool vs_injected = env->hvip & (1ULL << cause) & env->hvien && !(env->mip & (1ULL << cause)); + bool smode_double_trap = false; + uint64_t hdeleg = async ? env->hideleg : env->hedeleg; target_ulong tval = 0; target_ulong tinst = 0; target_ulong htval = 0; @@ -2088,6 +2091,30 @@ void riscv_cpu_do_interrupt(CPUState *cs) mode = env->priv <= PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M; + vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) || vs_injected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv == PRV_S && mode == PRV_S) { + bool dte = (env->menvcfg & MENVCFG_DTE) != 0; + bool sdt = (env->mstatus & MSTATUS_SDT) != 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte = (env->henvcfg & HENVCFG_DTE) != 0; + } else if (env->virt_enabled) { + /* VS -> HS, use mstatus_hs */ + sdt = (env->mstatus_hs & MSTATUS_SDT) != 0; + } + } + smode_double_trap = dte && sdt; + if (smode_double_trap) { + mode = PRV_M; + } + } + if (mode == PRV_S) { /* handle the trap in S-mode */ /* save elp status */ @@ -2096,10 +2123,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg = async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt @@ -2132,6 +2156,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s = set_field(s, MSTATUS_SDT, 1); + } env->mstatus = s; sxlen = 16 << riscv_cpu_sxl(env); env->scause = cause | ((target_ulong)async << (sxlen - 1)); @@ -2184,9 +2211,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MIE, 0); env->mstatus = s; env->mcause = cause | ((target_ulong)async << (mxlen - 1)); + if (smode_double_trap) { + env->mtval2 = env->mcause; + env->mcause = RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 = mtval2; + } env->mepc = env->pc; env->mtval = tval; - env->mtval2 = mtval2; env->mtinst = tinst; /*