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Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH v7 RESEND 1/5] hw/core/machine: Reject thread level cache Date: Fri, 10 Jan 2025 22:51:11 +0800 Message-Id: <20250110145115.1574345-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250110145115.1574345-1-zhao1.liu@intel.com> References: <20250110145115.1574345-1-zhao1.liu@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.432, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently, neither i386 nor ARM have real hardware support for per- thread cache, and there is no clear demand for this specific cache topology. Additionally, since ARM even can't support this special cache topology in device tree, it is unnecessary to support it at this moment, even though per-thread cache might have potential scheduling benefits for VMs without CPU affinity. Therefore, disable thread-level cache topology in the general machine part. At present, i386 has not enabled SMP cache, so disabling the thread parameter does not pose compatibility issues. In the future, if there is a clear demand for this feature, the correct approach would be to add a new control field in MachineClass.smp_props and enable it only for the machines that require it. Signed-off-by: Zhao Liu --- Changes since Patch v6: * New commit to reject "thread" parameter when parse smp-cache. --- hw/core/machine-smp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index b954eb849027..4e020c358b66 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -321,6 +321,13 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } + if (props->topology == CPU_TOPOLOGY_LEVEL_THREAD) { + error_setg(errp, + "%s level cache not supported by this machine", + CpuTopologyLevel_str(props->topology)); + return false; + } + if (!machine_check_topo_support(ms, props->topology, errp)) { return false; }