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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc0babsm90587775e9.14.2025.01.10.08.02.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 9/9] hw/arm/stellaris: Wire GPTM[#n] output to ADC input #n Date: Fri, 10 Jan 2025 17:02:04 +0100 Message-ID: <20250110160204.74997-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The ADC model is very simple, and only consider the 4 GPTM IRQs as trigger. Currently they are all wired to the same input IRQ. This is a QDev design mistake. We could use a OR_IRQ, but the ADC actually really has one input for each GPTM, so have the ADC create 4 inputs and wire each GPTM output to them. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index c89522332e2..446d6595a6d 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -701,8 +701,16 @@ static void stellaris_i2c_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -/* Analogue to Digital Converter. This is only partially implemented, - enough for applications that use a combined ADC and timer tick. */ +/* + * Analogue to Digital Converter. + * + * Each of the 4 trigger inputs has a MUX for 5 inputs + * (see Stellaris Data Sheet Figure 11-1: "ADC Module Block Diagram"). + * + * This model only consider the GPTM inputs, thus MUX is not implemented. + */ + +#define STELLARIS_ADC_TRIGGERS 4 #define STELLARIS_ADC_EM_CONTROLLER 0 #define STELLARIS_ADC_EM_COMP 1 @@ -986,7 +994,7 @@ static void stellaris_adc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, "adc", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); + qdev_init_gpio_in(dev, stellaris_adc_trigger, STELLARIS_ADC_TRIGGERS); } /* Board init. */ @@ -1061,7 +1069,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) DeviceState *gpio_dev[NUM_GPIO], *nvic; qemu_irq gpio_in[NUM_GPIO][8]; qemu_irq gpio_out[NUM_GPIO][8]; - qemu_irq adc; + DeviceState *adc; int sram_size; int flash_size; DeviceState *i2c_dev[NUM_I2C]; @@ -1144,15 +1152,12 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); if (DEV_CAP(1, ADC)) { - dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, + adc = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), qdev_get_gpio_in(nvic, 15), qdev_get_gpio_in(nvic, 16), qdev_get_gpio_in(nvic, 17), NULL); - adc = qdev_get_gpio_in(dev, 0); - } else { - adc = NULL; } for (i = 0; i < NUM_GPTM; i++) { if (DEV_CAP(2, GPTM(i))) { @@ -1166,9 +1171,12 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); + /* TODO: This is incorrect, but we get away with it because the ADC output is only ever pulsed. */ - qdev_connect_gpio_out(dev, 0, adc); + if (adc) { + qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(adc, i)); + } } }