| Message ID | 20250126072056.4004912-12-antonb@tenstorrent.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Fix some RISC-V instruction corner cases | expand |
Reviewed-by: Max Chou <max.chou@sifive.com> On 2025/1/26 3:20 PM, Anton Blanchard wrote: > Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> > --- > target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 312d8b1b81..2741f8bd8e 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2410,10 +2410,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) > } > > /* OPFVF with WIDEN */ > -#define GEN_OPFVF_WIDEN_TRANS(NAME) \ > +#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \ > static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > { \ > - if (opfvf_widen_check(s, a)) { \ > + if (CHECK(s, a)) { \ > uint32_t data = 0; \ > static gen_helper_opfvf *const fns[2] = { \ > gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ > @@ -2429,8 +2429,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > return false; \ > } > > -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) > +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check) > > static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) > { > @@ -2512,7 +2512,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) > > /* Vector Widening Floating-Point Multiply */ > GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) > -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf) > +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check) > > /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ > GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) > @@ -2537,10 +2537,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check) > GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) > GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) > GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) > -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) > +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check) > > /* Vector Floating-Point Square-Root Instruction */ >
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 312d8b1b81..2741f8bd8e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2410,10 +2410,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) } /* OPFVF with WIDEN */ -#define GEN_OPFVF_WIDEN_TRANS(NAME) \ +#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opfvf_widen_check(s, a)) { \ + if (CHECK(s, a)) { \ uint32_t data = 0; \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ @@ -2429,8 +2429,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ return false; \ } -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf) -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { @@ -2512,7 +2512,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) /* Vector Widening Floating-Point Multiply */ GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf) +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check) /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) @@ -2537,10 +2537,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check) /* Vector Floating-Point Square-Root Instruction */
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)