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Sat, 25 Jan 2025 23:22:15 -0800 (PST) Received: from ausc-rvsw-c-01-anton.tenstorrent.com ([38.104.49.66]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2b28f1d887csm1814281fac.29.2025.01.25.23.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jan 2025 23:22:15 -0800 (PST) From: Anton Blanchard To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Anton Blanchard , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap Date: Sun, 26 Jan 2025 07:20:51 +0000 Message-Id: <20250126072056.4004912-8-antonb@tenstorrent.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250126072056.4004912-1-antonb@tenstorrent.com> References: <20250126072056.4004912-1-antonb@tenstorrent.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=antonb@tenstorrent.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 0952bcbe2c..bc22b42801 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -458,13 +458,14 @@ static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) * instruction cannot overlap the source mask register (v0). * (Section 5.3) */ -static bool vext_wide_check_common(DisasContext *s, int vd, int vm) +static bool vext_wide_check_common(DisasContext *s, int vd, int vs, int vm) { return (s->lmul <= 2) && (s->sew < MO_64) && ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) && require_align(vd, s->lmul + 1) && - require_vm(vm, vd); + require_vm(vm, vd) && + require_vm(vm, vs); } /* @@ -498,14 +499,14 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm) { - return vext_wide_check_common(s, vd, vm) && + return vext_wide_check_common(s, vd, vs, vm) && require_align(vs, s->lmul) && require_noover(vd, s->lmul + 1, vs, s->lmul); } static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) { - return vext_wide_check_common(s, vd, vm) && + return vext_wide_check_common(s, vd, vs, vm) && require_align(vs, s->lmul + 1); }