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Thu, 06 Feb 2025 10:27:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IEFv0yp6Pc/17tva9qeYrjmWryHjjb8YNY48mesuOMfENJWxQ+RpIT6xhMdNRBcgzkuWqpZJw== X-Received: by 2002:a7b:c319:0:b0:434:f586:7520 with SMTP id 5b1f17b1804b1-43924a27e47mr4459935e9.6.1738866441856; Thu, 06 Feb 2025 10:27:21 -0800 (PST) Received: from [192.168.1.84] ([93.56.163.127]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391da9656fsm28597865e9.3.2025.02.06.10.27.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 10:27:20 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 04/22] target/riscv: merge riscv_cpu_class_init with the class_base function Date: Thu, 6 Feb 2025 19:26:52 +0100 Message-ID: <20250206182711.2420505-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250206182711.2420505-1-pbonzini@redhat.com> References: <20250206182711.2420505-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 803b2a7c3f4..baf4dd017b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2961,15 +2961,18 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data) } else { mcc->def = g_new0(RISCVCPUDef, 1); } -} -static void riscv_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - RISCVCPUDef *def = data; + if (data) { + RISCVCPUDef *def = data; + if (def->misa_mxl_max) { + assert(def->misa_mxl_max <= MXL_RV128); + mcc->def->misa_mxl_max = def->misa_mxl_max; + } + } - mcc->def->misa_mxl_max = def->misa_mxl_max; - riscv_cpu_validate_misa_mxl(mcc); + if (!object_class_is_abstract(c)) { + riscv_cpu_validate_misa_mxl(mcc); + } } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, @@ -3069,7 +3072,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_DYNAMIC_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &((RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }), \ @@ -3080,7 +3082,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_VENDOR_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &((RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }), \ @@ -3091,7 +3092,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &((RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }), \ @@ -3102,7 +3102,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &((RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }), \