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helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. STRUCT_FIELD is introduced here because I am not sure it is needed; it is a bit ugly and I wanted not to have it in the patch that introduces cpu_cfg_fields.h.inc. I don't really understand why satp_mode is included in RISCVCPUConfig; therefore, the end of the series includes a patch to move satp_mode directly in RISCVCPU, thus removing the need for STRUCT_FIELD; it can be moved before this one in a non-RFC posting. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 6 ++++ target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_cfg_fields.h.inc | 6 +++- target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++- 4 files changed, 59 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f757f0b6210..9b25c0c889b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -519,6 +519,12 @@ struct ArchCPU { typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; + int priv_spec; + int32_t vext_spec; + int satp_mode32; + int satp_mode64; + RISCVCPUConfig cfg; } RISCVCPUDef; /** diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ad02693fa66..07789a9de88 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -39,6 +39,7 @@ typedef struct { struct RISCVCPUConfig { #define BOOL_FIELD(x) bool x; #define TYPED_FIELD(type, x) type x; +#define STRUCT_FIELD(type, x) type x; #include "cpu_cfg_fields.h.inc" }; diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index 56fffb5f177..cbedf0a703b 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -4,6 +4,9 @@ #ifndef TYPED_FIELD #define TYPED_FIELD(type, x) #endif +#ifndef STRUCT_FIELD +#define STRUCT_FIELD(type, x) +#endif BOOL_FIELD(ext_zba) BOOL_FIELD(ext_zbb) @@ -160,8 +163,9 @@ TYPED_FIELD(uint16_t, cbop_blocksize) TYPED_FIELD(uint16_t, cboz_blocksize) #ifndef CONFIG_USER_ONLY -TYPED_FIELD(RISCVSATPMap, satp_mode); +STRUCT_FIELD(RISCVSATPMap, satp_mode) #endif #undef BOOL_FIELD #undef TYPED_FIELD +#undef STRUCT_FIELD diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index baf4dd017b2..1d999488465 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -74,6 +74,15 @@ bool riscv_cpu_option_set(const char *optname) return g_hash_table_contains(general_user_opts, optname); } +static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, RISCVCPUConfig *src) +{ +#define BOOL_FIELD(x) dest->x |= src->x; +#define TYPED_FIELD(type, x) if (src->x) dest->x = src->x; + /* only satp_mode, which is initialized by instance_init */ +#define STRUCT_FIELD(type, x) +#include "cpu_cfg_fields.h.inc" +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} @@ -432,7 +441,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) } static void set_satp_mode_max_supported(RISCVCPU *cpu, - uint8_t satp_mode) + int satp_mode) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; @@ -1476,6 +1485,24 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbop_blocksize = 64; cpu->cfg.cboz_blocksize = 64; cpu->env.vext_ver = VEXT_VERSION_1_00_0; + + env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext; + riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); + + if (mcc->def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.priv_ver = mcc->def->priv_spec; + } + if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.vext_ver = mcc->def->vext_spec; + } +#ifndef CONFIG_USER_ONLY + if (riscv_cpu_mxl(env) == MXL_RV32 && mcc->def->satp_mode32 != RISCV_PROFILE_ATTR_UNUSED) { + set_satp_mode_max_supported(RISCV_CPU(obj), mcc->def->satp_mode32); + } + if (riscv_cpu_mxl(env) >= MXL_RV64 && mcc->def->satp_mode64 != RISCV_PROFILE_ATTR_UNUSED) { + set_satp_mode_max_supported(RISCV_CPU(obj), mcc->def->satp_mode64); + } +#endif } static void riscv_bare_cpu_init(Object *obj) @@ -2968,6 +2995,25 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data) assert(def->misa_mxl_max <= MXL_RV128); mcc->def->misa_mxl_max = def->misa_mxl_max; } + if (def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) { + assert(def->priv_spec <= PRIV_VERSION_LATEST); + mcc->def->priv_spec = def->priv_spec; + } + if (def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) { + assert(def->vext_spec != 0); + mcc->def->vext_spec = def->vext_spec; + } + if (def->satp_mode32 != RISCV_PROFILE_ATTR_UNUSED) { + assert(def->satp_mode32 <= VM_1_10_SV32); + mcc->def->satp_mode32 = def->satp_mode32; + } + if (def->satp_mode64 != RISCV_PROFILE_ATTR_UNUSED) { + assert(def->satp_mode64 <= VM_1_10_SV64); + mcc->def->satp_mode64 = def->satp_mode64; + } + mcc->def->misa_ext |= def->misa_ext; + + riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); } if (!object_class_is_abstract(c)) {