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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent profile mechanism. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 61 +++++++++++++++++++++++++++++----------------- 2 files changed, 40 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1363a081c30..66ce72f7d41 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -519,6 +519,7 @@ struct ArchCPU { typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUProfile *profile; uint32_t misa_ext; int priv_spec; int32_t vext_spec; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1cb091ddb0c..253ed5132c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1486,6 +1486,10 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cboz_blocksize = 64; cpu->env.vext_ver = VEXT_VERSION_1_00_0; + if (mcc->def->profile) { + mcc->def->profile->enabled = true; + } + env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); @@ -2868,22 +2872,6 @@ static const Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), }; -#if defined(TARGET_RISCV64) -static void rva22u64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22U64.enabled = true; -} - -static void rva22s64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22S64.enabled = true; -} -#endif - static const gchar *riscv_gdb_arch_name(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -2950,6 +2938,22 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } +static bool profile_has_parent(RISCVCPUProfile *trial, RISCVCPUProfile *parent) +{ + if (!parent) { + return true; + } + + while (parent != trial) { + trial = trial->parent; + if (!trial) { + return false; + } + } + + return true; +} + static void riscv_cpu_class_base_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -2964,6 +2968,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data) if (data) { RISCVCPUDef *def = data; mcc->def->bare |= def->bare; + if (def->profile) { + assert(profile_has_parent(def->profile, mcc->def->profile)); + assert(mcc->def->bare); + mcc->def->profile = def->profile; + } if (def->misa_mxl_max) { assert(def->misa_mxl_max <= MXL_RV128); mcc->def->misa_mxl_max = def->misa_mxl_max; @@ -3130,16 +3139,23 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) }), \ } -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ +#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name = (type_name), \ - .parent = TYPE_RISCV_BARE_CPU, \ - .instance_init = (initfn), \ + .parent = (parent_type_name), \ .class_data = &((RISCVCPUDef) { \ - .misa_mxl_max = (misa_mxl_max_), \ + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \ + .satp_mode32 = RISCV_PROFILE_ATTR_UNUSED, \ + .satp_mode64 = RISCV_PROFILE_ATTR_UNUSED, \ + __VA_ARGS__ \ }), \ } +#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \ + DEFINE_RISCV_CPU(type_name, parent_type_name, \ + .profile = &(profile_)) + static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_RISCV_CPU, @@ -3215,8 +3231,9 @@ static const TypeInfo riscv_cpu_type_infos[] = { #endif /* CONFIG_TCG */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), + + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64), #endif /* TARGET_RISCV64 */ };