[PULL,09/32] hw/core/machine: Reject thread level cache

Commit Message

Philippe Mathieu-Daudé Feb. 10, 2025, 8:41 p.m. UTC

From: Zhao Liu <[e-mail]>

Currently, neither i386 nor ARM have real hardware support for per-
thread cache, and there is no clear demand for this specific cache
topology.

Additionally, since ARM even can't support this special cache topology
in device tree, it is unnecessary to support it at this moment, even
though per-thread cache might have potential scheduling benefits for
VMs without CPU affinity.

Therefore, disable thread-level cache topology in the general machine
part. At present, i386 has not enabled SMP cache, so disabling the
thread parameter does not pose compatibility issues.

In the future, if there is a clear demand for this feature, the correct
approach would be to add a new control field in MachineClass.smp_props
and enable it only for the machines that require it.

Signed-off-by: Zhao Liu <[e-mail]>
Reviewed-by: Michael S. Tsirkin <[e-mail]>
Reviewed-by: Philippe Mathieu-Daudé <[e-mail]>
Message-ID: <[e-mail]>
Signed-off-by: Philippe Mathieu-Daudé <[e-mail]>
---
 hw/core/machine-smp.c | 7 +++++++
 1 file changed, 7 insertions(+)

Patch

diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index b954eb84902..4e020c358b6 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -321,6 +321,13 @@  bool machine_parse_smp_cache(MachineState *ms,
             return false;
         }
 
+        if (props->topology == CPU_TOPOLOGY_LEVEL_THREAD) {
+            error_setg(errp,
+                       "%s level cache not supported by this machine",
+                       CpuTopologyLevel_str(props->topology));
+            return false;
+        }
+
         if (!machine_check_topo_support(ms, props->topology, errp)) {
             return false;
         }