| Message ID | 20250216024709.2624325-3-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: minor cleanups | expand |
On 16/2/25 03:47, Richard Henderson wrote: > These defines never should have been added as they were > never used. Only 32-bit hosts may have these opcodes and > they have them unconditionally. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/loongarch64/tcg-target-has.h | 2 -- > tcg/riscv/tcg-target-has.h | 2 -- > 2 files changed, 4 deletions(-) > > diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h > index ac88522eef..188b00799f 100644 > --- a/tcg/loongarch64/tcg-target-has.h > +++ b/tcg/loongarch64/tcg-target-has.h > @@ -37,8 +37,6 @@ > #define TCG_TARGET_HAS_clz_i32 1 > #define TCG_TARGET_HAS_ctz_i32 1 > #define TCG_TARGET_HAS_ctpop_i32 0 > -#define TCG_TARGET_HAS_brcond2 0 > -#define TCG_TARGET_HAS_setcond2 0 > #define TCG_TARGET_HAS_qemu_st8_i32 0 Fixes: 6cb14e4de29 ("tcg/loongarch64: Add the tcg-target.h file") Missed in 0a16d036154 ("tcg/loongarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'") > diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h > index f35f9b31f5..98081084f2 100644 > --- a/tcg/riscv/tcg-target-has.h > +++ b/tcg/riscv/tcg-target-has.h > @@ -37,8 +37,6 @@ > #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) > #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) > #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) > -#define TCG_TARGET_HAS_brcond2 1 > -#define TCG_TARGET_HAS_setcond2 1 > #define TCG_TARGET_HAS_qemu_st8_i32 0 Fixes: fb1f70f3685 ("tcg/riscv: Add the tcg-target.h file") Missed in 0242532b45d ("tcg/riscv: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On Sun, Feb 16, 2025 at 12:49 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > These defines never should have been added as they were > never used. Only 32-bit hosts may have these opcodes and > they have them unconditionally. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/loongarch64/tcg-target-has.h | 2 -- > tcg/riscv/tcg-target-has.h | 2 -- > 2 files changed, 4 deletions(-) > > diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h > index ac88522eef..188b00799f 100644 > --- a/tcg/loongarch64/tcg-target-has.h > +++ b/tcg/loongarch64/tcg-target-has.h > @@ -37,8 +37,6 @@ > #define TCG_TARGET_HAS_clz_i32 1 > #define TCG_TARGET_HAS_ctz_i32 1 > #define TCG_TARGET_HAS_ctpop_i32 0 > -#define TCG_TARGET_HAS_brcond2 0 > -#define TCG_TARGET_HAS_setcond2 0 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > > /* 64-bit operations */ > diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h > index f35f9b31f5..98081084f2 100644 > --- a/tcg/riscv/tcg-target-has.h > +++ b/tcg/riscv/tcg-target-has.h > @@ -37,8 +37,6 @@ > #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) > #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) > #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) > -#define TCG_TARGET_HAS_brcond2 1 > -#define TCG_TARGET_HAS_setcond2 1 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > > #define TCG_TARGET_HAS_negsetcond_i64 1 > -- > 2.43.0 > >
diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h index ac88522eef..188b00799f 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -37,8 +37,6 @@ #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_brcond2 0 -#define TCG_TARGET_HAS_setcond2 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 /* 64-bit operations */ diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index f35f9b31f5..98081084f2 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -37,8 +37,6 @@ #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) -#define TCG_TARGET_HAS_brcond2 1 -#define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_negsetcond_i64 1
These defines never should have been added as they were never used. Only 32-bit hosts may have these opcodes and they have them unconditionally. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/riscv/tcg-target-has.h | 2 -- 2 files changed, 4 deletions(-)