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Wed, 19 Feb 2025 10:46:43 -0800 (PST) Date: Wed, 19 Feb 2025 10:46:03 -0800 In-Reply-To: <20250219184609.1839281-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20250219184609.1839281-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250219184609.1839281-13-wuhaotsh@google.com> Subject: [PATCH v5 12/17] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, chli30@nuvoton.corp-partner.google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, philmd@linaro.org Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3Eye2ZwgKCn4ywjcqvujiqqing.eqosgow-fgxgnpqpipw.qti@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org These 2 values are different between NPCM7XX and NPCM8XX CLKs. So we add them to the class and assign different values to them. Reviewed-by: Peter Maydell Signed-off-by: Hao Wu --- hw/misc/npcm_clk.c | 18 ++++++++++++------ hw/misc/npcm_gcr.c | 2 ++ include/hw/misc/npcm_clk.h | 9 ++++++++- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 0ecf0df3bb..78144b14e3 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -81,7 +81,7 @@ enum NPCM7xxCLKRegisters { * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on * core domain reset, but this reset type is not yet supported by QEMU. */ -static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = { +static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] = { [NPCM7XX_CLK_CLKEN1] = 0xffffffff, [NPCM7XX_CLK_CLKSEL] = 0x004aaaaa, [NPCM7XX_CLK_CLKDIV1] = 0x5413f855, @@ -728,10 +728,11 @@ static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size) { uint32_t reg = offset / sizeof(uint32_t); NPCMCLKState *s = opaque; + NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s); int64_t now_ns; uint32_t value = 0; - if (reg >= NPCM7XX_CLK_NR_REGS) { + if (reg >= c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -776,11 +777,12 @@ static void npcm_clk_write(void *opaque, hwaddr offset, { uint32_t reg = offset / sizeof(uint32_t); NPCMCLKState *s = opaque; + NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s); uint32_t value = v; trace_npcm_clk_write(offset, value); - if (reg >= NPCM7XX_CLK_NR_REGS) { + if (reg >= c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -870,10 +872,10 @@ static const struct MemoryRegionOps npcm_clk_ops = { static void npcm_clk_enter_reset(Object *obj, ResetType type) { NPCMCLKState *s = NPCM_CLK(obj); + NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s); - QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); - - memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); + g_assert(sizeof(s->regs) >= c->nr_regs * sizeof(uint32_t)); + memcpy(s->regs, c->cold_reset_values, sizeof(s->regs)); s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); npcm7xx_clk_update_all_clocks(s); /* @@ -1045,11 +1047,14 @@ static void npcm_clk_class_init(ObjectClass *klass, void *data) static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) { + NPCMCLKClass *c = NPCM_CLK_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS); dc->desc = "NPCM7xx Clock Control Registers"; + c->nr_regs = NPCM7XX_CLK_NR_REGS; + c->cold_reset_values = npcm7xx_cold_reset_values; } static const TypeInfo npcm7xx_clk_pll_info = { @@ -1081,6 +1086,7 @@ static const TypeInfo npcm_clk_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(NPCMCLKState), .instance_init = npcm_clk_init, + .class_size = sizeof(NPCMCLKClass), .class_init = npcm_clk_class_init, .abstract = true, }; diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index ec16ea620e..4e8ce2cb89 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -215,6 +215,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size) break; case 8: + g_assert(!(reg & 1)); value = deposit64(s->regs[reg], 32, 32, s->regs[reg + 1]); break; @@ -270,6 +271,7 @@ static void npcm_gcr_write(void *opaque, hwaddr offset, break; case 8: + g_assert(!(reg & 1)); s->regs[reg] = value; s->regs[reg + 1] = extract64(v, 32, 32); break; diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index db03b46a52..f47614ac8d 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -175,8 +175,15 @@ struct NPCMCLKState { Clock *clkref; }; +typedef struct NPCMCLKClass { + SysBusDeviceClass parent; + + size_t nr_regs; + const uint32_t *cold_reset_values; +} NPCMCLKClass; + #define TYPE_NPCM_CLK "npcm-clk" -OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK) +OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" #endif /* NPCM_CLK_H */