diff mbox series

[PULL,25/41] roms: Update vbootrom to 1287b6e

Message ID	20250220162123.626941-26-peter.maydell@linaro.org (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 25/41] roms: Update vbootrom to 1287b6e Date: Thu, 20 Feb 2025 16:21:06 +0000 Message-ID: <20250220162123.626941-26-peter.maydell@linaro.org> In-Reply-To: <20250220162123.626941-1-peter.maydell@linaro.org> References: <20250220162123.626941-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS__EL1 from EL2 and NS EL1 \| expand [PULL,01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS__EL1 from EL2 and NS EL1 [PULL,02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS [PULL,03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 [PULL,04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 [PULL,05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps [PULL,06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 [PULL,07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes [PULL,08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() [PULL,09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult [PULL,10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 [PULL,11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps [PULL,12/41] target/arm: Remove CP_ACCESS_TRAP handling [PULL,13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED [PULL,14/41] target/arm: Correct errors in WFI/WFE trapping [PULL,15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition [PULL,16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs [PULL,17/41] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs [PULL,18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL [PULL,19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs [PULL,20/41] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs [PULL,21/41] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs [PULL,22/41] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs [PULL,23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX [PULL,24/41] target/arm: Use uint32_t in t32_expandimm_imm() [PULL,25/41] roms: Update vbootrom to 1287b6e [PULL,26/41] pc-bios: Add NPCM8XX vBootrom [PULL,27/41] hw/ssi: Make flash size a property in NPCM7XX FIU [PULL,28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr [PULL,29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR [PULL,30/41] hw/misc: Add nr_regs and cold_reset_values to NPCM GCR [PULL,31/41] hw/misc: Add support for NPCM8XX GCR [PULL,32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module [PULL,33/41] hw/misc: Support 8-bytes memop in NPCM GCR module [PULL,34/41] hw/misc: Rename npcm7xx_clk to npcm_clk [PULL,35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK [PULL,36/41] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK [PULL,37/41] hw/misc: Support NPCM8XX CLK Module Registers [PULL,38/41] hw/net: Add NPCM8XX PCS Module [PULL,39/41] hw/arm: Add NPCM8XX SoC [PULL,40/41] hw/arm: Add NPCM845 Evaluation board [PULL,41/41] docs/system/arm: Add Description for NPCM8XX SoC

Commit Message

Peter Maydell Feb. 20, 2025, 4:21 p.m. UTC

From: Hao Wu <wuhaotsh@google.com>

This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.

We updated the npcm7xx bootrom to be compiled from this version.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
 roms/vbootrom               |   2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/pc-bios/npcm7xx_bootrom.bin b/pc-bios/npcm7xx_bootrom.bin
index 38f89d1b97b0c2e133af2a9fbed0521be132065b..903f126636f9ef5d1100c056656ccfb2b32e5e10 100644
GIT binary patch
delta 90
zcmZo*Yhc^(l+nU*!D9x6DNkDr=09a-2ztoGz`#|*F#jn7L;r()|Np;c0m>C1$z?$0
Ywog`Ma%Vh0Ig_b-VgU<}A_D>d06Rh+WdHyG

delta 69
zcmZo*Yhc^(lu^NO!D9x2$xoRb7CdZGnE#ZCA@Cs+0|QqL!~CZV4E+!GPG)41X52Pe
SmdTy*+~icIZXQJj1ONb5*AzJb

diff --git a/roms/vbootrom b/roms/vbootrom
index 0c37a43527f..1287b6e42e8 160000
--- a/roms/vbootrom
+++ b/roms/vbootrom
@@ -1 +1 @@ 
-Subproject commit 0c37a43527f0ee2b9584e7fb2fdc805e902635ac
+Subproject commit 1287b6e42e839ba2ab0f06268c5b53ae60df3537