| Message ID | 20250221122623.495188-3-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv/kvm: reset time changes | expand |
On Fri, Feb 21, 2025 at 09:26:22AM -0300, Daniel Henrique Barboza wrote: > We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but > in no particular order and missing some of them (like env->mstatus). > > Create a helper to do that, unclogging reset_vcpu(), and initialize > env->mstatus as well. Keep the regs in the same order they appear in > struct kvm_riscv_csr from the KVM UAPI, similar to what > kvm_riscv_(get|put)_regs_csr are doing. This will make a bit easier to > add new KVM CSRs and to verify which values we're writing back to KVM > during vcpu reset. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++-------- > 1 file changed, 15 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 484b6afe7c..f14fcc58bb 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -605,6 +605,19 @@ static int kvm_riscv_put_regs_core(CPUState *cs) > return ret; > } > > +static void kvm_riscv_reset_regs_csr(CPURISCVState *env) > +{ > + env->mstatus = 0; > + env->mie = 0; > + env->stvec = 0; > + env->sscratch = 0; > + env->sepc = 0; > + env->scause = 0; > + env->stval = 0; > + env->mip = 0; > + env->satp = 0; > +} > + > static int kvm_riscv_get_regs_csr(CPUState *cs) > { > CPURISCVState *env = &RISCV_CPU(cs)->env; > @@ -1609,14 +1622,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > env->pc = cpu->env.kernel_addr; > env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ > env->gpr[11] = cpu->env.fdt_addr; /* a1 */ > - env->satp = 0; > - env->mie = 0; > - env->stvec = 0; > - env->sscratch = 0; > - env->sepc = 0; > - env->scause = 0; > - env->stval = 0; > - env->mip = 0; > + > + kvm_riscv_reset_regs_csr(env); > } > > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > -- > 2.48.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 484b6afe7c..f14fcc58bb 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -605,6 +605,19 @@ static int kvm_riscv_put_regs_core(CPUState *cs) return ret; } +static void kvm_riscv_reset_regs_csr(CPURISCVState *env) +{ + env->mstatus = 0; + env->mie = 0; + env->stvec = 0; + env->sscratch = 0; + env->sepc = 0; + env->scause = 0; + env->stval = 0; + env->mip = 0; + env->satp = 0; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { CPURISCVState *env = &RISCV_CPU(cs)->env; @@ -1609,14 +1622,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) env->pc = cpu->env.kernel_addr; env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ env->gpr[11] = cpu->env.fdt_addr; /* a1 */ - env->satp = 0; - env->mie = 0; - env->stvec = 0; - env->sscratch = 0; - env->sepc = 0; - env->scause = 0; - env->stval = 0; - env->mip = 0; + + kvm_riscv_reset_regs_csr(env); } void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but in no particular order and missing some of them (like env->mstatus). Create a helper to do that, unclogging reset_vcpu(), and initialize env->mstatus as well. Keep the regs in the same order they appear in struct kvm_riscv_csr from the KVM UAPI, similar to what kvm_riscv_(get|put)_regs_csr are doing. This will make a bit easier to add new KVM CSRs and to verify which values we're writing back to KVM during vcpu reset. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-)