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Mon, 24 Feb 2025 00:24:40 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:40 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN Date: Mon, 24 Feb 2025 16:24:10 +0800 Message-Id: <20250224082417.31382-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of Smstateen extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c7318f64cf12..d421c7a1b65d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -135,6 +135,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, #define RISCV_AIA_CSR_REG(name) \ (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name)) +#define RISCV_SMSTATEEN_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ @@ -687,10 +690,31 @@ static int kvm_riscv_put_regs_aia_csr(CPUState *cs) return 0; } +static int kvm_riscv_get_regs_smstateen_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_GET_CSR(cs, env, + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]); + + return 0; +} + +static int kvm_riscv_put_regs_smstateen_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_SET_CSR(cs, env, + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]); + + return 0; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { kvm_riscv_get_regs_general_csr(cs); kvm_riscv_get_regs_aia_csr(cs); + kvm_riscv_get_regs_smstateen_csr(cs); return 0; } @@ -699,6 +723,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) { kvm_riscv_put_regs_general_csr(cs); kvm_riscv_put_regs_aia_csr(cs); + kvm_riscv_put_regs_smstateen_csr(cs); return 0; }