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Mon, 24 Feb 2025 19:40:23 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:19 +0000 Subject: [PATCH v2 6/9] target/loongarch: Fix some modifiers for log formatting MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-6-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org target_ulong -> TARGET_FMT_ld vaddr -> VADDR_PRIx uint32_t -> PRIx32 Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/loongarch/tcg/translate.c | 5 ++--- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc index c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1..8584441b543712af8a56aa234c90fd6370c8df01 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -56,7 +56,7 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) { qemu_log_mask(LOG_GUEST_ERROR, "Warning: source register overlaps destination register" - "in atomic insn at pc=0x" TARGET_FMT_lx "\n", + "in atomic insn at pc=0x%016"VADDR_PRIx"\n", ctx->base.pc_next - 4); return false; } diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 97f38fc391338ba4b76115b142fa76d89e45cd62..a1426b46f36c99e300ab924cb487875ec21ab226 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -517,7 +517,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base, if (unlikely((level == 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, - "Attepted LDDIR with level %"PRId64"\n", level); + "Attepted LDDIR with level "TARGET_FMT_ld"\n", level); return base; } diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 1fca4afc731c048816618d87610a0cc0fe7579b1..3939670e18d01bd9fc08861532166882fbd3f890 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -287,9 +287,8 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next); if (!decode(ctx, ctx->opcode)) { - qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " - TARGET_FMT_lx ": 0x%x\n", - ctx->base.pc_next, ctx->opcode); + qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. %016"VADDR_PRIx + ": 0x%08"PRIx32"\n", ctx->base.pc_next, ctx->opcode); generate_exception(ctx, EXCCODE_INE); }