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Mon, 24 Feb 2025 19:40:25 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:21 +0000 Subject: [PATCH v2 8/9] target/loongarch: Fix load type for gen_ll MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-8-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.149; envelope-from=jiaxun.yang@flygoat.com; helo=fout-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is in TCGv which means it should be a tl type value. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc index 8584441b543712af8a56aa234c90fd6370c8df01..138bcb3e9999b2c186057c658a019136311f1b82 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv t0 = make_address_i(ctx, src1, a->imm); - tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop); tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval)); gen_set_gpr(a->rd, t1, EXT_NONE);