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Fri, 28 Feb 2025 12:05:07 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:50 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-5-whendrik@google.com> Subject: [PATCH v6 5/8] i386: Add CPUID enumeration for RDT From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=38xbCZwgKCm4iTQZPdUWSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--whendrik.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wuethrich --- include/hw/i386/rdt.h | 23 +++++++++++++ target/i386/cpu.c | 75 +++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++ 3 files changed, 103 insertions(+) diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index b63b433eef..a21bf804a6 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -29,8 +29,31 @@ #define RDT_MAX_L2_MASK_COUNT 63 #define RDT_MAX_MBA_THRTL_COUNT 63 +/* RDT L3 Cache Monitoring Technology */ +#define CPUID_F_0_EDX_L3 (1U << 1) +#define CPUID_F_1_EDX_L3_OCCUPANCY (1U << 0) +#define CPUID_F_1_EDX_L3_TOTAL_BW (1U << 1) +#define CPUID_F_1_EDX_L3_LOCAL_BW (1U << 2) + +/* RDT Cache Allocation Technology */ +#define CPUID_10_0_EBX_L3_CAT (1U << 1) +#define CPUID_10_0_EBX_L2_CAT (1U << 2) +#define CPUID_10_0_EBX_MBA (1U << 3) + +/* RDT L3 Allocation features */ +#define CPUID_10_1_EAX_CBM_LENGTH 0xf +#define CPUID_10_1_EBX_CBM 0x0 +#define CPUID_10_1_ECX_CDP 0x0 /* to enable, it would be (1U << 2) */ #define CPUID_10_1_EDX_COS_MAX RDT_MAX_L3_MASK_COUNT + +/* RDT L2 Allocation features*/ +#define CPUID_10_2_EAX_CBM_LENGTH 0xf +#define CPUID_10_2_EBX_CBM 0x0 #define CPUID_10_2_EDX_COS_MAX RDT_MAX_L2_MASK_COUNT + +/* RDT MBA features */ +#define CPUID_10_3_EAX_THRTL_MAX 89 +#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2) #define CPUID_10_3_EDX_COS_MAX RDT_MAX_MBA_THRTL_COUNT typedef struct RDTState RDTState; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 72ab147e85..cd06744451 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -42,6 +42,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "hw/i386/rdt.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -6869,6 +6870,80 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ break; +#ifndef CONFIG_USER_ONLY + case 0xF: + /* Shared Resource Monitoring Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; +#ifdef CONFIG_RDT + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM)) + break; + if (!(cpu->rdtStatePerL3Cache)) { + warn_report("Intel RDT features enabled in commandline, " + "but rdt device not used"); + break; + } + /* Non-zero count is ResId */ + switch (count) { + /* Monitoring Resource Type Enumeration */ + case 0: + *edx = env->features[FEAT_RDT_F_0_EDX]; + *ebx = rdt_max_rmid(cpu->rdtStatePerL3Cache); + break; + case 1: + *ebx = 1; + *ecx = rdt_max_rmid(cpu->rdtStatePerL3Cache); + *edx = CPUID_F_1_EDX_L3_OCCUPANCY | + CPUID_F_1_EDX_L3_TOTAL_BW | + CPUID_F_1_EDX_L3_LOCAL_BW; + break; + } +#endif + break; + case 0x10: + /* Shared Resource Director Technology Allocation Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; +#ifdef CONFIG_RDT + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE)) + break; + if (!(cpu->rdtPerCore)) { + warn_report("Intel RDT features enabled in commandline, " + "but rdt device not used"); + break; + } + /* Non-zero count is ResId */ + switch (count) { + /* Cache Allocation Technology Available Resource Types */ + case 0: + *ebx = CPUID_10_0_EBX_L3_CAT | + CPUID_10_0_EBX_L2_CAT | + CPUID_10_0_EBX_MBA; + break; + case 1: + *eax = CPUID_10_1_EAX_CBM_LENGTH; + *ebx = CPUID_10_1_EBX_CBM; + *ecx = CPUID_10_1_ECX_CDP; + *edx = CPUID_10_1_EDX_COS_MAX; + break; + case 2: + *eax = CPUID_10_2_EAX_CBM_LENGTH; + *ebx = CPUID_10_2_EBX_CBM; + *edx = CPUID_10_2_EDX_COS_MAX; + break; + case 3: + *eax = CPUID_10_3_EAX_THRTL_MAX; + *ecx = CPUID_10_3_ECX_LINEAR_RESPONSE; + *edx = CPUID_10_3_EDX_COS_MAX; + break; + } +#endif + break; +#endif case 0x1C: if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 08089ce6c2..6f5a3ecbd4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -679,6 +679,7 @@ typedef enum FeatureWord { FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */ + FEAT_RDT_F_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ FEATURE_WORDS, } FeatureWord; @@ -853,8 +854,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_EBX_RTM (1U << 11) /* Zero out FPU CS and FPU DS */ #define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13) +/* Resource Director Technology Monitoring */ +#define CPUID_7_0_EBX_PQM (1U << 12) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) +/* Resource Director Technology Allocation */ +#define CPUID_7_0_EBX_PQE (1U << 15) /* AVX-512 Foundation */ #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Doubleword & Quadword Instruction */