@@ -82,6 +82,14 @@ typedef struct CPUArchState {
target_ulong stack_start;
uint8_t slot_cancelled;
+
+#ifndef CONFIG_USER_ONLY
+ /* Some system registers are per thread and some are global. */
+ target_ulong t_sreg[NUM_SREGS];
+ target_ulong *g_sreg;
+
+ target_ulong greg[NUM_GREGS];
+#endif
target_ulong new_value_usr;
MemLog mem_log_stores[STORES_MAX];
@@ -288,6 +288,14 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
/* Default NaN value: sign bit set, all frac bits set */
set_float_default_nan_pattern(0b11111111, &env->fp_status);
+
+#ifndef CONFIG_USER_ONLY
+ if (cs->cpu_index == 0) {
+ memset(env->g_sreg, 0, sizeof(target_ulong) * NUM_SREGS);
+ }
+ memset(env->t_sreg, 0, sizeof(target_ulong) * NUM_SREGS);
+ memset(env->greg, 0, sizeof(target_ulong) * NUM_GREGS);
+#endif
}
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
@@ -313,6 +321,15 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
qemu_init_vcpu(cs);
cpu_reset(cs);
+#ifndef CONFIG_USER_ONLY
+ if (cs->cpu_index == 0) {
+ env->g_sreg = g_new0(target_ulong, NUM_SREGS);
+ } else {
+ CPUState *cpu0 = qemu_get_cpu(0);
+ CPUHexagonState *env0 = cpu_env(cpu0);
+ env->g_sreg = env0->g_sreg;
+ }
+#endif
mcc->parent_realize(dev, errp);
}