From patchwork Sat Mar 1 05:26:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13997310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9ABA9C282CD for ; Sat, 1 Mar 2025 05:28:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1toFNx-0003P2-Ru; Sat, 01 Mar 2025 00:27:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFNu-0003EO-7X for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:27:34 -0500 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFNs-00089a-HW for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:27:33 -0500 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5213ME9l026214 for ; Sat, 1 Mar 2025 05:27:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= aQTpOx5jqbkaYQSeOyg1RDpdSK2rWsfTHjWehLqh3+M=; b=bmZALErylwPU8kcw kPbAJ6GBAi56+s8KMg3biEkfhgH2sflrn2L8HYO+DVkXFzoHkl3l5+CM8dveF3b4 Rc5BJLqMDRZC+4wqQfyTNEQZTSi/C356OHzd8p1p4zmunSL7HIHGGN1CGG8MsmEW HN/s/C46zstCB1Qmx8DsohF/8pwOe1K4DZzk13J9YVM2tEtSLh27xeoedepnkfz3 /EJRBnugA7GV0HWLf/SsIQQDVwGeCM72lDmqIqukxssJau231KziTVrDEnxfqRIl fot7VQVXIOEYwLe18gSJ+RBmEkojxXc62iczu7Wj9ktJxt9RYCUkSVuoqux/uEMx oIeRow== Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 453t95r63f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Sat, 01 Mar 2025 05:27:21 +0000 (GMT) Received: by mail-pj1-f70.google.com with SMTP id 98e67ed59e1d1-2feb8d29740so3584999a91.1 for ; Fri, 28 Feb 2025 21:27:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740806840; x=1741411640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aQTpOx5jqbkaYQSeOyg1RDpdSK2rWsfTHjWehLqh3+M=; b=qaZlX2Gt7RnBr2KkX2+drWseId0iQXdrNCiVaD/MDqFPnjz17xjJRtJz2rlkMYB/ZQ Aa5LLESWde7Nh21BAOPeDdZrwSDbiFxfQLfG1iX5bwhquSBGA+eRljK35SeHF6WNuNcZ byS3Va17gkJA4Sn05NLgtkQUU2/TYnPALcusF7smR4gRM+rWAMXUfDSlpblH8HOhNFuk MYIO4PXHEyKp8rOhg6WmRAB+gr3SxvHng6cLms2WL0Ti9p6GNZU/Rnupj5/CmJKWcum2 wn/Ib0ro3fP7lDm82OMSYp2JYt7XXzOpPshYlAaSJj2+yiTQVgq+u/EMY20TGvk17kOL jiVQ== X-Gm-Message-State: AOJu0Yy0OcC8pWmIADqfRV+n3Fm34ibbteB4PZiOow5nFLbikLVEk6aV gHzJu5POppbsou6myvtCiX4De1LT+D+fc+asEeJ41nV/oVyrMhNglxuP9e8i4d57V2onLo+OBie jf1rcsoHhpnFOYdgm4Dqgp1L9PhQ3T4MTuIpM8VabqnP6iJG9GCM6G4HtcJx3ZQ== X-Gm-Gg: ASbGncs33O15dp06lWIVJGMNjToDv8e9MDNf7C4QAZ3wrE9MMv0A94A6ighWeXsbpW6 kYJV0Crk9xVbV4/+YzWcT2DXnQYIop3mvD1AHXrvqNdFKmryh3BXBT1mBW5xeMA2BpzYR5Ay951 ksv7wr9WL1oVUQJa3odn8AlK/sJJw2gIkwZhDt4I3WHN16dY1F5m6CvPO89kWxT1w86iT9QwedR 25nYupTISNQMg2WUhB46PQIXuGBW0zUgLBQOVWbNli5ozv7RO32RMkK5IPSaXXA7jnUNasNsdpq JFFCRxZc5/Hmzsm+ETgsR8s73uUxp/AMG1Il8KPihUNCKJvQH/1fZqu1Hqqd530F X-Received: by 2002:a17:90b:4ad0:b0:2ee:3cc1:793a with SMTP id 98e67ed59e1d1-2febac09ee9mr9420916a91.29.1740806839958; Fri, 28 Feb 2025 21:27:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IHsUQFyF3MrxCACgY5QBBnV23g1xxoF9xObq4gzbORba9PpjObTckEWzm4gvFnYJ7StwL0B6A== X-Received: by 2002:a17:90b:4ad0:b0:2ee:3cc1:793a with SMTP id 98e67ed59e1d1-2febac09ee9mr9420893a91.29.1740806839545; Fri, 28 Feb 2025 21:27:19 -0800 (PST) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe825bb346sm6930596a91.18.2025.02.28.21.27.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:27:19 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, Brian Cain Subject: [PATCH 24/38] target/hexagon: Add TCG overrides for int handler insts Date: Fri, 28 Feb 2025 21:26:14 -0800 Message-Id: <20250301052628.1011210-25-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> References: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: YhL_XjbopryT-Lje7pxTF-YCBub4Hmnx X-Proofpoint-GUID: YhL_XjbopryT-Lje7pxTF-YCBub4Hmnx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 phishscore=0 mlxlogscore=680 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010039 Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Brian Cain Define TCG overrides for {c,}swi {c,s}iad, iassign{r,w}, {s,g}etimask instructions. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 25 ++++++++++++++++++++++ target/hexagon/helper.h | 8 ++++++++ target/hexagon/op_helper.c | 40 ++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 362703ab45..642ca3d3ff 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/target/hexagon/gen_tcg_sys.h @@ -7,6 +7,31 @@ #ifndef HEXAGON_GEN_TCG_SYS_H #define HEXAGON_GEN_TCG_SYS_H +/* System mode instructions */ +#define fGEN_TCG_Y2_swi(SHORTCODE) \ + gen_helper_swi(tcg_env, RsV) + +#define fGEN_TCG_Y2_cswi(SHORTCODE) \ + gen_helper_cswi(tcg_env, RsV) + +#define fGEN_TCG_Y2_ciad(SHORTCODE) \ + gen_helper_ciad(tcg_env, RsV) + +#define fGEN_TCG_Y4_siad(SHORTCODE) \ + gen_helper_siad(tcg_env, RsV) + +#define fGEN_TCG_Y2_iassignw(SHORTCODE) \ + gen_helper_iassignw(tcg_env, RsV) + +#define fGEN_TCG_Y2_iassignr(SHORTCODE) \ + gen_helper_iassignr(RdV, tcg_env, RsV) + +#define fGEN_TCG_Y2_getimask(SHORTCODE) \ + gen_helper_getimask(RdV, tcg_env, RsV) + +#define fGEN_TCG_Y2_setimask(SHORTCODE) \ + gen_helper_setimask(tcg_env, PtV, RsV) + #define fGEN_TCG_Y2_setprio(SHORTCODE) \ gen_helper_setprio(tcg_env, PtV, RsV) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 146f4f02e4..2fe4440ddc 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -109,6 +109,14 @@ DEF_HELPER_2(probe_hvx_stores, void, env, int) DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int) #if !defined(CONFIG_USER_ONLY) +DEF_HELPER_2(swi, void, env, i32) +DEF_HELPER_2(cswi, void, env, i32) +DEF_HELPER_2(ciad, void, env, i32) +DEF_HELPER_2(siad, void, env, i32) +DEF_HELPER_2(iassignw, void, env, i32) +DEF_HELPER_2(iassignr, i32, env, i32) +DEF_HELPER_2(getimask, i32, env, i32) +DEF_HELPER_3(setimask, void, env, i32, i32) DEF_HELPER_2(sreg_read, i32, env, i32) DEF_HELPER_2(sreg_read_pair, i64, env, i32) DEF_HELPER_2(greg_read, i32, env, i32) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 865e8ebb3c..575f3fb163 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1337,6 +1337,46 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_t uiV) } #ifndef CONFIG_USER_ONLY +void HELPER(ciad)(CPUHexagonState *env, uint32_t mask) +{ + g_assert_not_reached(); +} + +void HELPER(siad)(CPUHexagonState *env, uint32_t mask) +{ + g_assert_not_reached(); +} + +void HELPER(swi)(CPUHexagonState *env, uint32_t mask) +{ + g_assert_not_reached(); +} + +void HELPER(cswi)(CPUHexagonState *env, uint32_t mask) +{ + g_assert_not_reached(); +} + +void HELPER(iassignw)(CPUHexagonState *env, uint32_t src) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(iassignr)(CPUHexagonState *env, uint32_t src) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(getimask)(CPUHexagonState *env, uint32_t tid) +{ + g_assert_not_reached(); +} + +void HELPER(setimask)(CPUHexagonState *env, uint32_t pred, uint32_t imask) +{ + g_assert_not_reached(); +} + void HELPER(sreg_write)(CPUHexagonState *env, uint32_t reg, uint32_t val) { g_assert_not_reached();