[29/38] target/hexagon: Add locks, id, next_PC to state

Commit Message

Brian Cain March 1, 2025, 5:26 a.m. UTC

From: Brian Cain <[e-mail]>

Signed-off-by: Brian Cain <[e-mail]>
---
 target/hexagon/cpu.h     | 37 +++++++++++++++++++++++++++++++++++--
 target/hexagon/cpu.c     |  6 ++++++
 target/hexagon/machine.c |  4 ++++
 3 files changed, 45 insertions(+), 2 deletions(-)

Patch

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index b7789a3c90..fb66151ac9 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -40,10 +40,37 @@ 
 #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
 #define VSTORES_MAX 2
 
+#ifndef CONFIG_USER_ONLY
+#define CPU_INTERRUPT_SWI      CPU_INTERRUPT_TGT_INT_0
+#define CPU_INTERRUPT_K0_UNLOCK CPU_INTERRUPT_TGT_INT_1
+#define CPU_INTERRUPT_TLB_UNLOCK CPU_INTERRUPT_TGT_INT_2
+
+#define HEX_CPU_MODE_USER    1
+#define HEX_CPU_MODE_GUEST   2
+#define HEX_CPU_MODE_MONITOR 3
+
+#define HEX_EXE_MODE_OFF     1
+#define HEX_EXE_MODE_RUN     2
+#define HEX_EXE_MODE_WAIT    3
+#define HEX_EXE_MODE_DEBUG   4
+#endif
+
+#define MMU_USER_IDX         0
+#ifndef CONFIG_USER_ONLY
+#define MMU_GUEST_IDX        1
+#define MMU_KERNEL_IDX       2
+
+typedef enum {
+    HEX_LOCK_UNLOCKED       = 0,
+    HEX_LOCK_WAITING        = 1,
+    HEX_LOCK_OWNER          = 2,
+    HEX_LOCK_QUEUED        = 3
+} hex_lock_state_t;
+#endif
+
+
 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
 
-#define MMU_USER_IDX 0
-
 typedef struct {
     target_ulong va;
     uint8_t width;
@@ -89,6 +116,12 @@  typedef struct CPUArchState {
     target_ulong *g_sreg;
 
     target_ulong greg[NUM_GREGS];
+
+    /* This alias of CPUState.cpu_index is used by imported sources: */
+    target_ulong threadId;
+    hex_lock_state_t tlb_lock_state;
+    hex_lock_state_t k0_lock_state;
+    target_ulong next_PC;
 #endif
     target_ulong new_value_usr;
 
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 2b6a707fca..908339c052 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -303,6 +303,12 @@  static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
         arch_set_system_reg(env, HEX_SREG_MODECTL, 0x1);
     }
     arch_set_system_reg(env, HEX_SREG_HTID, cs->cpu_index);
+    memset(env->t_sreg, 0, sizeof(target_ulong) * NUM_SREGS);
+    memset(env->greg, 0, sizeof(target_ulong) * NUM_GREGS);
+    env->threadId = cs->cpu_index;
+    env->tlb_lock_state = HEX_LOCK_UNLOCKED;
+    env->k0_lock_state = HEX_LOCK_UNLOCKED;
+    env->next_PC = 0;
 #endif
 }
 
diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c
index d9d71edf77..dc900422f4 100644
--- a/target/hexagon/machine.c
+++ b/target/hexagon/machine.c
@@ -19,6 +19,10 @@  const VMStateDescription vmstate_hexagon_cpu = {
         VMSTATE_UINTTL_ARRAY(env.pred, HexagonCPU, NUM_PREGS),
         VMSTATE_UINTTL_ARRAY(env.t_sreg, HexagonCPU, NUM_SREGS),
         VMSTATE_UINTTL_ARRAY(env.greg, HexagonCPU, NUM_GREGS),
+        VMSTATE_UINTTL(env.next_PC, HexagonCPU),
+        VMSTATE_UINTTL(env.tlb_lock_state, HexagonCPU),
+        VMSTATE_UINTTL(env.k0_lock_state, HexagonCPU),
+        VMSTATE_UINTTL(env.threadId, HexagonCPU),
         VMSTATE_END_OF_LIST()
     },
 };