From patchwork Sat Mar 1 05:26:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13997358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AB90C021B8 for ; Sat, 1 Mar 2025 05:35:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1toFOQ-0004fP-2K; Sat, 01 Mar 2025 00:28:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFOJ-0004KZ-If for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:27:59 -0500 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFOE-0008CC-5p for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:27:59 -0500 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5213M2ib025866 for ; Sat, 1 Mar 2025 05:27:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 835oOMFo4CsDJaMbZygdINbgfblYWGB5ivSAProI0aU=; b=Z/XbGw82A+zBR4ls w5PAaGluOl+DqmLZcQKbR4lI5hr1X5fghB4/L39/P5yuIdeKPCgyEL9RNuPGfP/m bHlvB3D1Z19WzX7/aKfvJ0IWi5hgRyDL5zhkfTtuWauF9zCuR5hOD7B3VME8O/9C UFf62IBhHS1VLXa6t9Ii+4zE8UUV7S6g4rj/a2kAgnnOMRxHoVGShhAAiUU4CXWp iv8Ov8L979hu1mmlfhU8rpq5VAkKQS2KNAha7GI31wMGu4u0ksX0JslLoI6nfdgC 7xcwf72k+u3l28IoGzhkRb0hSxSZPBG7Ct5s9w3GqbSJFb4AIfHP+yCR+Kmztqp0 41DTRQ== Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 453t95r648-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Sat, 01 Mar 2025 05:27:42 +0000 (GMT) Received: by mail-pj1-f70.google.com with SMTP id 98e67ed59e1d1-2feb47c6757so3927775a91.3 for ; Fri, 28 Feb 2025 21:27:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740806852; x=1741411652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=835oOMFo4CsDJaMbZygdINbgfblYWGB5ivSAProI0aU=; b=PzW+IHTv0WkCXHpFt8DYj+F1cRQC5J2UtVftp4VN/e91FLVxibNVPb+fWMNNHfbrcB mw+Lj6UDsKRve/aGnYsRwbp7BnPL2VPWkhWfw8q5nJxq8/tO2G4mgMtGlCcYQwBwJBAH BpqEEAhyICEW6sLHZwOWmXNS2OcXn7iT6yFL8TlRFoffioH+zFaNODb2KOviaXmiPGof EjFF68/ftToGi/BH821J1nlL2+Wf7JZ3T/n1Badj02DsOKHwc7HX7cihzys3lriiODwQ m2R+5RNQw+pEkw2+vC0nkmRF70k841TlUncYV6RbQHdrR8iue2nMbWGvBRI4nbJAJAH5 FfzA== X-Gm-Message-State: AOJu0YxEU+3fooeriwUeL8GzVxP0BrziQPZBL6cZ3VUZB+rLGDskcj8i Coh81VBnCtqke145qEfo6UCo/OgJa9urTVNTAws68XiuVAF0cABfzWMx8AfYwXyHbMhTKCcUz7D /R4ahWwbQY/zwbe9SVJYC0avuDNeWRpSiYWvcBnXaO0YAJBdE66iysqtWtIQvCg== X-Gm-Gg: ASbGncuz6xBSWt84t0TSIMLC5UEcekxhCUOCTeEL/YtGYdkXjQZljFuWwd0YgfinCk7 Ysr7/9rb1IO8uZuAm2x/BaEt+8lAF+5mKUYu6KzFr8qgxTK1di3XTe1t5X354bX9Y7rz9GiM03j 5OltPWAWzaQX/BrExYBS02FuIlQTZc+xyHLlSuyiqBvCg6gqjZkBbnEeNEsLM6SwwlQc/P4nvSO XCwpI7JIs/SXsXpAaIZeDUBwFivqRnv0pzFS1MB8hRcnJLJc2P17rveL+AfZXMUJP5+6Cx0XLxl 71do8gSAJdzJfl0W9xF5oID9rliz/h2sw6D96rnTSvKPNX2PnWtqA5mSm51ROpQb X-Received: by 2002:a17:90b:1ccb:b0:2fe:b470:dde4 with SMTP id 98e67ed59e1d1-2febab3c659mr11818921a91.12.1740806851599; Fri, 28 Feb 2025 21:27:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQ2NYOG8OHyWZSj20F0WzznMVi9CaK2ni8oFW6anHxiCdyN6Z1dXSur+TAOd9XCbm6AKtGXA== X-Received: by 2002:a17:90b:1ccb:b0:2fe:b470:dde4 with SMTP id 98e67ed59e1d1-2febab3c659mr11818882a91.12.1740806851110; Fri, 28 Feb 2025 21:27:31 -0800 (PST) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe825bb346sm6930596a91.18.2025.02.28.21.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:27:30 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, Brian Cain Subject: [PATCH 33/38] target/hexagon: Add gdb support for sys regs Date: Fri, 28 Feb 2025 21:26:23 -0800 Message-Id: <20250301052628.1011210-34-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> References: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: u2pzVOMp0i4cWnxhNMJegTqgxTWB0NBB X-Proofpoint-GUID: u2pzVOMp0i4cWnxhNMJegTqgxTWB0NBB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 phishscore=0 mlxlogscore=762 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010040 Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Brian Cain Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 6 ++ target/hexagon/internal.h | 4 ++ target/hexagon/cpu.c | 17 ++++++ target/hexagon/gdbstub.c | 45 ++++++++++++++ target/hexagon/op_helper.c | 16 +++++ gdb-xml/hexagon-sys.xml | 116 +++++++++++++++++++++++++++++++++++++ 6 files changed, 204 insertions(+) create mode 100644 gdb-xml/hexagon-sys.xml diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index ddc1158d8e..b0ccaf36f9 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -183,6 +183,12 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, uintptr_t pc); +#ifndef CONFIG_USER_ONLY +uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); +uint32_t hexagon_sreg_read(CPUHexagonState *env, uint32_t reg); +void hexagon_gdb_sreg_write(CPUHexagonState *env, uint32_t reg, uint32_t val); +#endif + static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 7cf7bcaa6c..c24c360921 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -22,6 +22,10 @@ int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +#endif int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int n); int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 7c34d015a3..34c39cecd9 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -29,6 +29,10 @@ #include "cpu_helper.h" #include "max.h" +#ifndef CONFIG_USER_ONLY +#include "sys_macros.h" +#endif + static void hexagon_v66_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } @@ -341,6 +345,12 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) hexagon_hvx_gdb_write_register, gdb_find_static_feature("hexagon-hvx.xml"), 0); +#ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, hexagon_sys_gdb_read_register, + hexagon_sys_gdb_write_register, + gdb_find_static_feature("hexagon-sys.xml"), 0); +#endif + qemu_init_vcpu(cs); cpu_reset(cs); #ifndef CONFIG_USER_ONLY @@ -400,6 +410,13 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) cc->tcg_ops = &hexagon_tcg_ops; } +#ifndef CONFIG_USER_ONLY +uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg) +{ + g_assert_not_reached(); +} +#endif + #define DEFINE_CPU(type_name, initfn) \ { \ .name = type_name, \ diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 12d6b3bbcb..8476199b75 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -76,6 +76,51 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) g_assert_not_reached(); } +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + CPUHexagonState *env = cpu_env(cs); + + if (n < NUM_SREGS) { + return gdb_get_regl(mem_buf, hexagon_sreg_read(env, n)); + } + n -= NUM_SREGS; + + if (n < NUM_GREGS) { + return gdb_get_regl(mem_buf, hexagon_greg_read(env, n)); + } + n -= NUM_GREGS; + + n -= TOTAL_PER_THREAD_REGS; + + if (n < NUM_PREGS) { + env->pred[n] = ldtul_p(mem_buf) & 0xff; + return sizeof(uint8_t); + } + + n -= NUM_PREGS; + + g_assert_not_reached(); +} + +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CPUHexagonState *env = cpu_env(cs); + + if (n < NUM_SREGS) { + hexagon_gdb_sreg_write(env, n, ldtul_p(mem_buf)); + return sizeof(target_ulong); + } + n -= NUM_SREGS; + + if (n < NUM_GREGS) { + return env->greg[n] = ldtul_p(mem_buf); + } + n -= NUM_GREGS; + + g_assert_not_reached(); +} +#endif static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n) { int total = 0; diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 76b2475d88..fd9caafefc 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1465,6 +1465,17 @@ void HELPER(sreg_write)(CPUHexagonState *env, uint32_t reg, uint32_t val) sreg_write(env, reg, val); } +void hexagon_gdb_sreg_write(CPUHexagonState *env, uint32_t reg, uint32_t val) +{ + BQL_LOCK_GUARD(); + sreg_write(env, reg, val); + /* + * The above is needed to run special logic for regs like syscfg, but it + * won't set read-only bits. This will: + */ + arch_set_system_reg(env, reg, val); +} + void HELPER(sreg_write_pair)(CPUHexagonState *env, uint32_t reg, uint64_t val) { BQL_LOCK_GUARD(); @@ -1508,6 +1519,11 @@ uint32_t HELPER(sreg_read)(CPUHexagonState *env, uint32_t reg) return sreg_read(env, reg); } +uint32_t hexagon_sreg_read(CPUHexagonState *env, uint32_t reg) +{ + return sreg_read(env, reg); +} + uint64_t HELPER(sreg_read_pair)(CPUHexagonState *env, uint32_t reg) { BQL_LOCK_GUARD(); diff --git a/gdb-xml/hexagon-sys.xml b/gdb-xml/hexagon-sys.xml new file mode 100644 index 0000000000..1d9c211722 --- /dev/null +++ b/gdb-xml/hexagon-sys.xml @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +