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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fea67a5dc8sm4732955a91.23.2025.02.28.21.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:29:04 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, Brian Cain Subject: [PATCH 11/39] target/hexagon: Add representation to count cycles Date: Fri, 28 Feb 2025 21:28:17 -0800 Message-Id: <20250301052845.1012069-12-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Bh_tzz09n2quIJ65z2U253K6-YARHKqF X-Proofpoint-GUID: Bh_tzz09n2quIJ65z2U253K6-YARHKqF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=851 mlxscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010040 Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Brian Cain The PCYCLE register can be enabled to indicate accumulated clock cycles. Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 3 ++- target/hexagon/cpu.c | 3 +++ target/hexagon/machine.c | 25 ++++++++++++++++++++++++- 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 1549c4f1f0..4b9c9873dc 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -113,7 +113,8 @@ typedef struct CPUArchState { target_ulong stack_start; uint8_t slot_cancelled; - + uint64_t t_cycle_count; + uint64_t *g_pcycle_base; #ifndef CONFIG_USER_ONLY /* Some system registers are per thread and some are global. */ target_ulong t_sreg[NUM_SREGS]; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 84a96a194b..89a051b41d 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -335,6 +335,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) if (cs->cpu_index == 0) { arch_set_system_reg(env, HEX_SREG_MODECTL, 0x1); + *(env->g_pcycle_base) = 0; } mmu_reset(env); arch_set_system_reg(env, HEX_SREG_HTID, cs->cpu_index); @@ -396,10 +397,12 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY if (cs->cpu_index == 0) { env->g_sreg = g_new0(target_ulong, NUM_SREGS); + env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base)); } else { CPUState *cpu0 = qemu_get_cpu(0); CPUHexagonState *env0 = cpu_env(cpu0); env->g_sreg = env0->g_sreg; + env->g_pcycle_base = env0->g_pcycle_base; } #endif diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index fcdbacf9fd..4baa22d51f 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -9,6 +9,27 @@ #include "cpu.h" #include "hex_mmu.h" +static int get_u64_ptr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field) +{ + uint64_t *p = pv; + *p = qemu_get_be64(f); + return 0; +} + +static int put_u64_ptr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + qemu_put_be64(f, *((uint64_t *)pv)); + return 0; +} + +const VMStateInfo vmstate_info_uint64_ptr = { + .name = "uint64_t_pointer", + .get = get_u64_ptr, + .put = put_u64_ptr, +}; + static int get_hex_tlb_ptr(QEMUFile *f, void *pv, size_t size, const VMStateField *field) { @@ -35,7 +56,6 @@ const VMStateInfo vmstate_info_hex_tlb_ptr = { .put = put_hex_tlb_ptr, }; - const VMStateDescription vmstate_hexagon_cpu = { .name = "cpu", .version_id = 0, @@ -56,6 +76,9 @@ const VMStateDescription vmstate_hexagon_cpu = { VMSTATE_UINTTL(env.wait_next_pc, HexagonCPU), VMSTATE_POINTER(env.hex_tlb, HexagonCPU, 0, vmstate_info_hex_tlb_ptr, CPUHexagonTLBContext *), + VMSTATE_UINT64(env.t_cycle_count, HexagonCPU), + VMSTATE_POINTER(env.g_pcycle_base, HexagonCPU, 0, + vmstate_info_uint64_ptr, uint64_t *), VMSTATE_END_OF_LIST() },