From patchwork Sat Mar 1 05:28:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13997353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CE46C021B8 for ; Sat, 1 Mar 2025 05:35:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1toFPx-0002F3-F8; Sat, 01 Mar 2025 00:29:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFPl-00013S-1I for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:29:29 -0500 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFPh-0008PX-Du for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:29:28 -0500 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5214o36a023030 for ; Sat, 1 Mar 2025 05:29:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Cro+9dSEynAsUdlc2d1xxFC9RibUn7LDydh+snlHwEU=; b=pc71sBrXnxhqMJpD VRjYrXUcBVNLHg+szKiaHUoLjVC7XmbED1CuLWme1TqPB8a9vM5GJqkyBQq6i1zA rP4JLrOHAAof4fb0BzxKZFgNfCGkGd42m5R6sJoNC8WkaSh5chTQImYpTNZVgtUI b3uQ4xaGV1TOBNie6UJBBRgZwswsi9cCm9w+/IgwVPFVtn3uOom1K7hHl7eI4AOl LUCBvfMdbVoMWI3lA0/qF0amDJawCUBsnQJ/FAtlyRm/c5PgglQuLOmHlLhPx8MO zZxnDXGi3jaSS0RydH2VbTqwU1SnDB9hrxw0ri+qJsTfEPxmGCkfdbetJHZqnjJJ gcFdkA== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 453uh701xx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Sat, 01 Mar 2025 05:29:14 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-2fec3e38c2dso3566442a91.2 for ; Fri, 28 Feb 2025 21:29:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740806953; x=1741411753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cro+9dSEynAsUdlc2d1xxFC9RibUn7LDydh+snlHwEU=; b=PZbaPHlGX9ic+3sAClrK0Cgk2FceT3lB84VnDvSn8YwKfAiOjuuOLvbYbqx1KHT9as yWYtFxaHoW6ZMzBfniZVD04ZY6UgjqOMhzVr/4ea2ESnKimGcWpq2YLDmOXvujBWxtVu uCHSm0Q9I2d4Cj5+e0ziX0Zegax+PsEwz42i03dySNik93wUdmdqArZpxoBGklZ5UnHf 29URCf4J7Ap0dv/Z3MHFuDWRzgQjBLypkZGuOWZ1jySyUnTb08mmWpsJzJPvRwDgrbor nIPB86C3/ORmFZ9jLWh0rPA5U+8S1eNuB7whAFRQZL+X4mB7GPpwL7t3iyCImWsMkBNV xtQg== X-Gm-Message-State: AOJu0YymmbGk8rCqw0DCot5Ht6kYh/n5SZ6QI6qMykRqDY5VjBy3lNB7 98YY/W5/DIpKjcYYjkHtRZCQBbpoxUA++Mw599rvXiy2UNFt5oObfeA3WwHB9LgCPiW1cj0rcvU n1jMp47oOv+lOJppQ5iN0iJ8iCgHseyO3y8Azq1KIWEn/UO7b9BpbAJQcNwkgKg== X-Gm-Gg: ASbGnctbm9J3ZNYIJsfAUk5bgevH5jQBQXjRCc8WxxpvdfQIM5IxjWz3qPqxMyMkdR4 5HZExi7IdhV2jBizQ6v4v2gTDpeXw5GvAdPrtSf0IDh/XTTdhdKQYoT+2ZVA6yBup9B5FGOWNgn PM+EG4lkfSZHJUV+w4oZscekDvvdp/8+k1iZsX50fdnhbmSeIx9fM+9LFvJZoY8RpZxEPzMfhvn c8pSGi2lnJJKDPXWAGrrPUHWuXP/TQVLS/lJF3fKTt9BQ1R7kQMMm9eKsp0hWB/j7VKXXnRbZQG Twqi0VCq9dkOsT4YwzO+T7MVmdit3Q3epLr3KK1p1e93Qj/PGKaSjdsMyzdnUtcw X-Received: by 2002:a17:90b:4c11:b0:2ee:db1a:2e3c with SMTP id 98e67ed59e1d1-2febab2eed3mr9322542a91.1.1740806953079; Fri, 28 Feb 2025 21:29:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IFeXbLV6sIZSMrvpiaStPg77h1Wefhvrh/Vnvz6lEyY90/Pziy7XdXXlS5GzckNJtlh3S7TwQ== X-Received: by 2002:a17:90b:4c11:b0:2ee:db1a:2e3c with SMTP id 98e67ed59e1d1-2febab2eed3mr9322516a91.1.1740806952707; Fri, 28 Feb 2025 21:29:12 -0800 (PST) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fea67a5dc8sm4732955a91.23.2025.02.28.21.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:29:12 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, Brian Cain Subject: [PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq Date: Fri, 28 Feb 2025 21:28:24 -0800 Message-Id: <20250301052845.1012069-19-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-GUID: v8IhRoPzkKyXxSbjeCqQ1tB2teQDxivj X-Proofpoint-ORIG-GUID: v8IhRoPzkKyXxSbjeCqQ1tB2teQDxivj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxscore=0 spamscore=0 malwarescore=0 mlxlogscore=934 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010040 Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 5 +++ target/hexagon/cpu.c | 73 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 045581d7be..d28c1249f3 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -207,6 +207,11 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uintptr_t pc); #ifndef CONFIG_USER_ONLY +/* + * @return true if the @a thread_env hardware thread is + * not stopped. + */ +bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); uint32_t hexagon_sreg_read(CPUHexagonState *env, uint32_t reg); void hexagon_gdb_sreg_write(CPUHexagonState *env, uint32_t reg, uint32_t val); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 843be8221f..e9f24581a6 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -31,6 +31,7 @@ #include "hex_mmu.h" #ifndef CONFIG_USER_ONLY +#include "macros.h" #include "sys_macros.h" #include "qemu/main-loop.h" #include "hex_interrupts.h" @@ -278,9 +279,28 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs, cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc; } +#ifndef CONFIG_USER_ONLY +bool hexagon_thread_is_enabled(CPUHexagonState *env) +{ + target_ulong modectl = arch_get_system_reg(env, HEX_SREG_MODECTL); + uint32_t thread_enabled_mask = GET_FIELD(MODECTL_E, modectl); + bool E_bit = thread_enabled_mask & (0x1 << env->threadId); + + return E_bit; +} +#endif + static bool hexagon_cpu_has_work(CPUState *cs) { +#ifndef CONFIG_USER_ONLY + CPUHexagonState *env = cpu_env(cs); + + return hexagon_thread_is_enabled(env) && + (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI + | CPU_INTERRUPT_K0_UNLOCK | CPU_INTERRUPT_TLB_UNLOCK)); +#else return true; +#endif } static void hexagon_restore_state_to_opc(CPUState *cs, @@ -411,19 +431,72 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +#if !defined(CONFIG_USER_ONLY) +static void hexagon_cpu_set_irq(void *opaque, int irq, int level) +{ + HexagonCPU *cpu = HEXAGON_CPU(opaque); + CPUState *cs = CPU(cpu); + CPUHexagonState *env = cpu_env(cs); + + switch (irq) { + case HEXAGON_CPU_IRQ_0 ... HEXAGON_CPU_IRQ_7: + qemu_log_mask(CPU_LOG_INT, "%s: irq %d, level %d\n", + __func__, irq, level); + if (level) { + hex_raise_interrupts(env, 1 << irq, CPU_INTERRUPT_HARD); + } + break; + default: + g_assert_not_reached(); + } +} +#endif + + static void hexagon_cpu_init(Object *obj) { +#if !defined(CONFIG_USER_ONLY) + HexagonCPU *cpu = HEXAGON_CPU(obj); + qdev_init_gpio_in(DEVICE(cpu), hexagon_cpu_set_irq, 8); +#endif } #include "hw/core/tcg-cpu-ops.h" +#ifndef CONFIG_USER_ONLY + +static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUHexagonState *env = cpu_env(cs); + if (interrupt_request & CPU_INTERRUPT_TLB_UNLOCK) { + cs->halted = false; + cpu_reset_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK); + return true; + } + if (interrupt_request & CPU_INTERRUPT_K0_UNLOCK) { + cs->halted = false; + cpu_reset_interrupt(cs, CPU_INTERRUPT_K0_UNLOCK); + return true; + } + if (interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI)) { + return hex_check_interrupts(env); + } + return false; +} + +#endif + static const TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .translate_code = hexagon_translate_code, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, +#if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt = hexagon_cpu_exec_interrupt, +#endif /* !CONFIG_USER_ONLY */ }; + static void hexagon_cpu_class_init(ObjectClass *c, void *data) { HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);