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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fea67a5dc8sm4732955a91.23.2025.02.28.21.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:29:40 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com Subject: [PATCH 39/39] target/hexagon: Add pcycle setting functionality Date: Fri, 28 Feb 2025 21:28:45 -0800 Message-Id: <20250301052845.1012069-40-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-GUID: RBjK4fBCfTX1B8BOYAX0sX9pHrND_-8S X-Proofpoint-ORIG-GUID: RBjK4fBCfTX1B8BOYAX0sX9pHrND_-8S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 mlxscore=0 suspectscore=0 bulkscore=0 impostorscore=0 mlxlogscore=544 priorityscore=1501 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010040 Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Brian Cain Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.c | 10 +++++++--- target/hexagon/cpu_helper.c | 17 ++++++++++++++--- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 80f5e23794..4ca6add834 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -440,19 +440,23 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) #endif qemu_init_vcpu(cs); -#ifndef CONFIG_USER_ONLY CPUHexagonState *env = cpu_env(cs); +#ifndef CONFIG_USER_ONLY hex_mmu_realize(env); if (cs->cpu_index == 0) { env->g_sreg = g_new0(target_ulong, NUM_SREGS); - env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base)); } else { CPUState *cpu0 = qemu_get_cpu(0); CPUHexagonState *env0 = cpu_env(cpu0); env->g_sreg = env0->g_sreg; - env->g_pcycle_base = env0->g_pcycle_base; } #endif + if (cs->cpu_index == 0) { + env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base)); + } else { + CPUState *cpu0 = qemu_get_cpu(0); + env->g_pcycle_base = cpu_env(cpu0)->g_pcycle_base; + } mcc->parent_realize(dev, errp); } diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 9c44cb7950..08c749e9fa 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -70,18 +70,29 @@ uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t cycles_hi) { - g_assert_not_reached(); + uint64_t cur_cycles = hexagon_get_sys_pcycle_count(env); + uint64_t cycles = + ((uint64_t)cycles_hi << 32) | extract64(cur_cycles, 0, 32); + hexagon_set_sys_pcycle_count(env, cycles); } void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t cycles_lo) { - g_assert_not_reached(); + uint64_t cur_cycles = hexagon_get_sys_pcycle_count(env); + uint64_t cycles = extract64(cur_cycles, 32, 32) | cycles_lo; + hexagon_set_sys_pcycle_count(env, cycles); } void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t cycles) { - g_assert_not_reached(); + *(env->g_pcycle_base) = cycles; + + CPUState *cs; + CPU_FOREACH(cs) { + CPUHexagonState *env_ = cpu_env(cs); + env_->t_cycle_count = 0; + } } static void set_wait_mode(CPUHexagonState *env)