@@ -1468,12 +1468,39 @@ void HELPER(resume)(CPUHexagonState *env, uint32_t mask)
uint32_t HELPER(getimask)(CPUHexagonState *env, uint32_t tid)
{
- g_assert_not_reached();
+ CPUState *cs;
+ CPU_FOREACH(cs) {
+ HexagonCPU *found_cpu = HEXAGON_CPU(cs);
+ CPUHexagonState *found_env = &found_cpu->env;
+ if (found_env->threadId == tid) {
+ target_ulong imask = arch_get_system_reg(found_env, HEX_SREG_IMASK);
+ qemu_log_mask(CPU_LOG_INT, "%s: tid %d imask = 0x%x\n",
+ __func__, env->threadId,
+ (unsigned)GET_FIELD(IMASK_MASK, imask));
+ return GET_FIELD(IMASK_MASK, imask);
+ }
+ }
+ return 0;
}
void HELPER(setimask)(CPUHexagonState *env, uint32_t pred, uint32_t imask)
{
- g_assert_not_reached();
+ CPUState *cs;
+
+ BQL_LOCK_GUARD();
+ CPU_FOREACH(cs) {
+ HexagonCPU *found_cpu = HEXAGON_CPU(cs);
+ CPUHexagonState *found_env = &found_cpu->env;
+
+ if (pred == found_env->threadId) {
+ SET_SYSTEM_FIELD(found_env, HEX_SREG_IMASK, IMASK_MASK, imask);
+ qemu_log_mask(CPU_LOG_INT, "%s: tid %d imask 0x%x\n",
+ __func__, found_env->threadId, imask);
+ hex_interrupt_update(env);
+ return;
+ }
+ }
+ hex_interrupt_update(env);
}
static bool handle_pmu_sreg_write(CPUHexagonState *env, uint32_t reg,