diff mbox series

[4/8] hw/hexagon: Add support for cfgbase

Message ID 20250301172045.1295412-5-brian.cain@oss.qualcomm.com (mailing list archive)
State New
Headers show
Series hexagon system emu, part 3/3 | expand

Commit Message

Brian Cain March 1, 2025, 5:20 p.m. UTC 
From: Sid Manning <sidneym@quicinc.com>

Signed-off-by: Sid Manning <sidneym@quicinc.com>
---
 target/hexagon/cpu.h     |  1 +
 hw/hexagon/hexagon_dsp.c | 10 ++++++++++
 target/hexagon/cpu.c     |  6 ++++++
 3 files changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 73c3bb34b0..0608d3265c 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -195,6 +195,7 @@  struct ArchCPU {
     uint32_t l2vic_base_addr;
     uint32_t hvx_contexts;
     uint32_t boot_addr;
+    uint64_t config_table_addr;
 #endif
 };
 
diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c
index 9f18cb6e3a..c4962a98bc 100644
--- a/hw/hexagon/hexagon_dsp.c
+++ b/hw/hexagon/hexagon_dsp.c
@@ -82,6 +82,12 @@  static void hexagon_common_init(MachineState *machine, Rev_t rev,
 
     MemoryRegion *address_space = get_system_memory();
 
+    MemoryRegion *config_table_rom = g_new(MemoryRegion, 1);
+    memory_region_init_rom(config_table_rom, NULL, "config_table.rom",
+                           sizeof(m_cfg->cfgtable), &error_fatal);
+    memory_region_add_subregion(address_space, m_cfg->cfgbase,
+                                config_table_rom);
+
     MemoryRegion *sram = g_new(MemoryRegion, 1);
     memory_region_init_ram(sram, NULL, "ddr.ram",
         machine->ram_size, &error_fatal);
@@ -130,6 +136,10 @@  static void hexagon_common_init(MachineState *machine, Rev_t rev,
         }
 
     }
+
+    rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
+                          sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
+                          &address_space_memory);
 }
 
 static void init_mc(MachineClass *mc)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 4ca6add834..34940e9a84 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -67,6 +67,8 @@  static const Property hexagon_cpu_properties[] = {
         0xffffffffULL),
     DEFINE_PROP_UINT32("hvx-contexts", HexagonCPU, hvx_contexts, 0),
     DEFINE_PROP_UINT32("exec-start-addr", HexagonCPU, boot_addr, 0xffffffffULL),
+    DEFINE_PROP_UINT64("config-table-addr", HexagonCPU, config_table_addr,
+                       0xffffffffULL),
 #endif
     DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),
     DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0,
@@ -361,6 +363,8 @@  void hexagon_cpu_soft_reset(CPUHexagonState *env)
 }
 #endif
 
+
+#define HEXAGON_CFG_ADDR_BASE(addr) (((addr) >> 16) & 0x0fffff)
 static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
 {
     CPUState *cs = CPU(obj);
@@ -401,6 +405,8 @@  static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
     env->wait_next_pc = 0;
     env->cause_code = -1;
     arch_set_thread_reg(env, HEX_REG_PC, cpu->boot_addr);
+    arch_set_system_reg(env, HEX_SREG_CFGBASE,
+                        HEXAGON_CFG_ADDR_BASE(cpu->config_table_addr));
 #endif
 }