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Mon, 03 Mar 2025 03:23:26 -0800 (PST) Received: from wheely.local0.net ([118.208.151.101]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223501f9e3bsm75388875ad.82.2025.03.03.03.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 03:23:25 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 2/3] target/ppc: Avoid work if MMU SPRs are written with same value Date: Mon, 3 Mar 2025 21:23:13 +1000 Message-ID: <20250303112315.586478-3-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250303112315.586478-1-npiggin@gmail.com> References: <20250303112315.586478-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=npiggin@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Avoid TLB flushing and hflags recomputation if LPCR, LPIDR, or PIDR are written with the same value. This is observed to happen in some cases (e.g., in hypervisor real-mode exit fastpath handlers). Signed-off-by: Nicholas Piggin --- target/ppc/cpu.c | 8 +++++++- target/ppc/misc_helper.c | 14 +++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index cdd50cb36d6..0fa2ccfcb2f 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -97,8 +97,14 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; + target_ulong old, new; - env->spr[SPR_LPCR] = val & pcc->lpcr_mask; + old = env->spr[SPR_LPCR]; + new = val & pcc->lpcr_mask; + if (old == new) { + return; + } + env->spr[SPR_LPCR] = new; /* The gtse bit affects hflags */ hreg_compute_hflags(env); diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 179e8b6b4d2..ac439e00326 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -403,12 +403,24 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val) void helper_store_pidr(CPUPPCState *env, target_ulong val) { + if (env->spr[SPR_BOOKS_PID] == (uint32_t)val) { + return; + } + env->spr[SPR_BOOKS_PID] = (uint32_t)val; - tlb_flush(env_cpu(env)); + + if (env->spr[SPR_LPCR] & LPCR_HR) { + /* PID is only relevant to CPU translations when LPCR[HR]=1 */ + tlb_flush(env_cpu(env)); + } } void helper_store_lpidr(CPUPPCState *env, target_ulong val) { + if (env->spr[SPR_LPIDR] == (uint32_t)val) { + return; + } + env->spr[SPR_LPIDR] = (uint32_t)val; /*